Simulation Results: rom_ctrl

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 96.30 %
  • assert
  • 95.34 %
  • func
  • 96.18 %
  • line
  • 99.32 %
  • branch
  • 97.08 %
  • cond
  • 92.42 %
  • toggle
  • 99.34 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.650s 309.167us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.540s 211.197us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.390s 2025.230us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.260s 3336.559us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 216.329us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.320s 389.380us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.390s 2025.230us 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 216.329us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.480s 1068.538us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.510s 789.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.450s 1002.899us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 29.870s 1102.121us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 16.700s 2027.304us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.100s 292.455us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.550s 726.626us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.550s 726.626us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.540s 211.197us 1 1 100.00
rom_ctrl_csr_rw 9.390s 2025.230us 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 216.329us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.890s 698.320us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.540s 211.197us 1 1 100.00
rom_ctrl_csr_rw 9.390s 2025.230us 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 216.329us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.890s 698.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.480s 1570.759us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 226.100s 1025.736us 0 1 0.00
rom_ctrl_tl_intg_err 96.160s 1805.637us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 226.100s 1025.736us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 226.100s 1025.736us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 226.100s 1025.736us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 226.100s 1025.736us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.650s 309.167us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.650s 309.167us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.650s 309.167us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 96.160s 1805.637us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
rom_ctrl_kmac_err_chk 16.700s 2027.304us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.640s 4778.407us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.480s 1570.759us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 226.100s 1025.736us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 23.280s 771.600us 1 1 100.00