Simulation Results: rstmgr

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.88 %
  • code
  • 99.21 %
  • assert
  • 97.44 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.200s 69.560us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.140s 91.677us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.830s 35.875us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.640s 146.304us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.210s 39.858us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.990s 66.884us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.830s 35.875us 1 1 100.00
rstmgr_csr_aliasing 1.210s 39.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.200s 160.399us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.910s 41.762us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.060s 84.537us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.610s 498.129us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.610s 498.129us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.610s 498.129us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.610s 498.129us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 29.050s 4547.535us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.820s 35.852us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.620s 43.474us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.620s 43.474us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.140s 91.677us 1 1 100.00
rstmgr_csr_rw 0.830s 35.875us 1 1 100.00
rstmgr_csr_aliasing 1.210s 39.858us 1 1 100.00
rstmgr_same_csr_outstanding 0.840s 38.729us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.140s 91.677us 1 1 100.00
rstmgr_csr_rw 0.830s 35.875us 1 1 100.00
rstmgr_csr_aliasing 1.210s 39.858us 1 1 100.00
rstmgr_same_csr_outstanding 0.840s 38.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.630s 6780.516us 1 1 100.00
rstmgr_tl_intg_err 5.700s 892.334us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.630s 6780.516us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.630s 6780.516us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 5.700s 892.334us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.970s 59.139us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.390s 448.602us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.970s 291.585us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.630s 6780.516us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 35.875us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 35.875us 1 1 100.00