Simulation Results: rv_dm

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.32 %
  • code
  • 72.26 %
  • assert
  • 96.16 %
  • func
  • 57.54 %
  • line
  • 90.58 %
  • branch
  • 74.57 %
  • cond
  • 73.68 %
  • toggle
  • 69.33 %
  • FSM
  • 53.12 %
Validation stages
V1
93.55%
V2
64.29%
V2S
83.33%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 1.780s 1066.588us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.840s 123.144us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.170s 373.646us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 3.100s 8345.733us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 2.700s 1105.260us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 22.160s 24580.365us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 1.710s 2019.388us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 33.970s 43946.621us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 38.940s 68521.761us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 0.860s 175.059us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.780s 1059.236us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.040s 1007.935us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.190s 272.948us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.810s 146.783us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.280s 2435.255us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.730s 128.292us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.000s 520.491us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 0.860s 175.059us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.920s 175.638us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.820s 529.470us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.040s 1007.935us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.950s 43.938us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.370s 216.298us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.730s 203.907us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 25.490s 7639.860us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 18.040s 1522.592us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.950s 88.499us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 18.040s 1522.592us 1 1 100.00
rv_dm_csr_rw 1.730s 203.907us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.700s 146.582us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.760s 33.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 1.780s 1066.588us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.440s 924.714us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 1.060s 493.986us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.810s 447.123us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.010s 320.055us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 304.000s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 537.470s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 176.090s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 555.660s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.900s 155.151us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 2.330s 2224.467us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.060s 249.367us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.800s 255.036us 0 1 0.00
tap_ctrl_transitions 1 2 50.00
rv_dm_tap_fsm_rand_reset 0.880s 42.133us 0 1 0.00
rv_dm_tap_fsm 8.700s 7974.686us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.830s 97.681us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.760s 300.790us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.800s 88.846us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 0.750s 48.542us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 0.750s 48.542us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 18.040s 1522.592us 1 1 100.00
rv_dm_csr_hw_reset 1.370s 216.298us 1 1 100.00
rv_dm_csr_rw 1.730s 203.907us 1 1 100.00
rv_dm_same_csr_outstanding 4.830s 177.219us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 18.040s 1522.592us 1 1 100.00
rv_dm_csr_hw_reset 1.370s 216.298us 1 1 100.00
rv_dm_csr_rw 1.730s 203.907us 1 1 100.00
rv_dm_same_csr_outstanding 4.830s 177.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 13.040s 1670.083us 1 1 100.00
rv_dm_sec_cm 3.700s 2377.279us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 13.040s 1670.083us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.330s 2224.467us 1 1 100.00
rv_dm_debug_disabled 0.780s 73.235us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.330s 2224.467us 1 1 100.00
rv_dm_debug_disabled 0.780s 73.235us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 1.780s 1066.588us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 0.910s 167.669us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.720s 128.663us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.720s 128.663us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 0.910s 167.669us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.900s 32.520us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 266.880s 300000.000us 0 1 0.00