Simulation Results: spi_device

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.98 %
  • code
  • 93.26 %
  • assert
  • 94.30 %
  • func
  • 76.39 %
  • line
  • 99.11 %
  • branch
  • 98.40 %
  • cond
  • 95.91 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 55.640s 17853.013us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.990s 39.865us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.990s 123.607us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 7.890s 373.995us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.740s 1211.740us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.070s 186.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.990s 123.607us 1 1 100.00
spi_device_csr_aliasing 15.740s 1211.740us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.610s 36.111us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.300s 161.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.990s 21.669us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.870s 1.374us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 3.319us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.000s 253.034us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.000s 253.034us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.160s 378.911us 1 1 100.00
spi_device_tpm_sts_read 0.750s 63.013us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 10.500s 1010.109us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.950s 2375.175us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.010s 2551.408us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.010s 2551.408us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.160s 1266.903us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.160s 1266.903us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.160s 1266.903us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.160s 1266.903us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.160s 1266.903us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.020s 463.569us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.090s 507.822us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.090s 507.822us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.090s 507.822us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.020s 311.767us 1 1 100.00
spi_device_read_buffer_direct 7.810s 1776.055us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.090s 507.822us 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 83.440s 10621.355us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.230s 204.744us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.230s 204.744us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 55.640s 17853.013us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 134.350s 315784.808us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 87.820s 9108.936us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.680s 18.588us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 23.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.640s 69.309us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.640s 69.309us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.990s 39.865us 1 1 100.00
spi_device_csr_rw 1.990s 123.607us 1 1 100.00
spi_device_csr_aliasing 15.740s 1211.740us 1 1 100.00
spi_device_same_csr_outstanding 2.120s 134.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.990s 39.865us 1 1 100.00
spi_device_csr_rw 1.990s 123.607us 1 1 100.00
spi_device_csr_aliasing 15.740s 1211.740us 1 1 100.00
spi_device_same_csr_outstanding 2.120s 134.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 8.200s 725.187us 1 1 100.00
spi_device_sec_cm 1.000s 65.182us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.200s 725.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 0.690s 12.734us 1 1 100.00