Simulation Results: spi_host

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.71 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 87.92 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 52.000s 15337.685us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 87.887us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 47.062us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 76.294us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 174.575us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 89.338us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 47.062us 1 1 100.00
spi_host_csr_aliasing 2.000s 174.575us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 34.775us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 31.855us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 94.159us 1 1 100.00
spi_host_error_cmd 2.000s 21.377us 1 1 100.00
spi_host_event 6.000s 1404.250us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 93.906us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 93.906us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 93.906us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 30.000s 2457.887us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 45.594us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 93.906us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 93.906us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 52.000s 15337.685us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 52.000s 15337.685us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 22.000s 1451.381us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 1222.576us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 53.000s 14456.769us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 861.687us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 94.159us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 50.468us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 19.679us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 337.504us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 337.504us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 87.887us 1 1 100.00
spi_host_csr_rw 2.000s 47.062us 1 1 100.00
spi_host_csr_aliasing 2.000s 174.575us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 55.759us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 87.887us 1 1 100.00
spi_host_csr_rw 2.000s 47.062us 1 1 100.00
spi_host_csr_aliasing 2.000s 174.575us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 55.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 371.933us 1 1 100.00
spi_host_tl_intg_err 1.000s 58.429us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 58.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 203.000s 5881.174us 1 1 100.00