Simulation Results: sram_ctrl

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.34 %
  • code
  • 93.73 %
  • assert
  • 95.79 %
  • func
  • 93.51 %
  • line
  • 98.51 %
  • branch
  • 96.46 %
  • cond
  • 92.53 %
  • toggle
  • 90.66 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 11.380s 217.959us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.710s 12.404us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.730s 42.903us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.710s 238.636us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 51.750us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.770s 47.276us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.730s 42.903us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 51.750us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.510s 721.480us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.090s 515.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 494.010s 7138.881us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 160.400s 30877.081us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 36.970s 765.743us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 406.720s 14229.230us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.710s 1182.570us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 756.480s 68568.577us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 38.180s 737.278us 1 1 100.00
sram_ctrl_partial_access_b2b 245.050s 4653.456us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 13.450s 321.713us 1 1 100.00
sram_ctrl_throughput_w_partial_write 32.750s 140.580us 1 1 100.00
sram_ctrl_throughput_w_readback 9.250s 145.853us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 252.640s 2343.031us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.880s 71.736us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1341.000s 292469.362us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.790s 15.385us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.050s 55.428us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.050s 55.428us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 12.404us 1 1 100.00
sram_ctrl_csr_rw 0.730s 42.903us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 51.750us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 46.144us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 12.404us 1 1 100.00
sram_ctrl_csr_rw 0.730s 42.903us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 51.750us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 46.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.520s 439.451us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.540s 160.825us 1 1 100.00
sram_ctrl_sec_cm 0.880s 39.394us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.880s 39.394us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.540s 160.825us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 252.640s 2343.031us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 252.640s 2343.031us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.730s 42.903us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 756.480s 68568.577us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 756.480s 68568.577us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 756.480s 68568.577us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.710s 1182.570us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.150s 95.877us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.520s 439.451us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.380s 57.252us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 11.380s 217.959us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 11.380s 217.959us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 756.480s 68568.577us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.880s 39.394us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.710s 1182.570us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.880s 39.394us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.880s 39.394us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 11.380s 217.959us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.880s 39.394us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 33.900s 2528.749us 1 1 100.00