Simulation Results: uart

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.77 %
  • code
  • 96.62 %
  • assert
  • 97.12 %
  • func
  • 42.58 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.32 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.900s 655.325us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.600s 49.866us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.650s 58.762us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.740s 278.631us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.610s 37.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.720s 39.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.650s 58.762us 1 1 100.00
uart_csr_aliasing 0.610s 37.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 80.390s 80431.778us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.900s 655.325us 1 1 100.00
uart_tx_rx 80.390s 80431.778us 1 1 100.00
parity_error 2 2 100.00
uart_intr 5.910s 9439.727us 1 1 100.00
uart_rx_parity_err 6.060s 6196.563us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 80.390s 80431.778us 1 1 100.00
uart_intr 5.910s 9439.727us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 15.240s 75505.092us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 23.760s 67776.144us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 10.600s 17015.211us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 5.910s 9439.727us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 5.910s 9439.727us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 5.910s 9439.727us 1 1 100.00
perf 1 1 100.00
uart_perf 317.640s 8605.999us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.690s 1518.413us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.690s 1518.413us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 94.200s 86495.426us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 47.970s 41874.433us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.010s 5233.381us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 29.980s 5584.455us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 79.460s 104258.638us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 58.490s 145299.144us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.560s 24.536us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.550s 14.216us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.430s 129.207us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.430s 129.207us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.600s 49.866us 1 1 100.00
uart_csr_rw 0.650s 58.762us 1 1 100.00
uart_csr_aliasing 0.610s 37.556us 1 1 100.00
uart_same_csr_outstanding 0.780s 18.184us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.600s 49.866us 1 1 100.00
uart_csr_rw 0.650s 58.762us 1 1 100.00
uart_csr_aliasing 0.610s 37.556us 1 1 100.00
uart_same_csr_outstanding 0.780s 18.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.690s 39.086us 1 1 100.00
uart_tl_intg_err 1.020s 331.359us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.020s 331.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 39.230s 6953.858us 1 1 100.00