Simulation Results: ac_range_check

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.37 %
  • code
  • 92.98 %
  • assert
  • 96.35 %
  • func
  • 57.79 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 80.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 30.000s 452.057us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 48.000s 2811.357us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 77.116us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 858.953us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 22.000s 989.598us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 4466.253us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 106.913us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 858.953us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 4466.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 5.000s 239.551us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 25.000s 5545.363us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 78.000s 14449.147us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 45.618us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 22.248us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 36.596us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 36.596us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 77.116us 1 1 100.00
ac_range_check_csr_rw 3.000s 858.953us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 4466.253us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 141.929us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 77.116us 1 1 100.00
ac_range_check_csr_rw 3.000s 858.953us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 4466.253us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 141.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 431.590us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 431.590us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 431.590us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 431.590us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 61.000s 10183.796us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 14.068us 1 1 100.00
ac_range_check_tl_intg_err 12.000s 637.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 241.000s 2284.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 27.000s 8170.527us 1 1 100.00