| chip_sw_spi_device_flash_mode |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
100.586s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through |
1 |
1 |
100.00 |
|
chip_sw_spi_device_pass_through |
1710.770s |
2987.479us |
1 |
1 |
100.00
|
| chip_sw_spi_device_pass_through_collision |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through_collision |
231.640s |
198.848us |
0 |
1 |
0.00
|
| chip_sw_spi_device_tpm |
0 |
1 |
0.00 |
|
chip_sw_spi_device_tpm |
32.007s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_spi_host_tx_rx |
27.299s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_host_tx_rx |
36.819s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_device_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_device_tx_rx |
26.017s |
0.000us |
0 |
1 |
0.00
|
| chip_pin_mux |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.890s |
0.000us |
0 |
1 |
0.00
|
| chip_padctrl_attributes |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.890s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_wake |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_wake |
142.459s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_retention |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_retention |
132.064s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_data_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
147.900s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_instruction_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
147.900s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_csr_rw |
0 |
1 |
0.00 |
|
chip_jtag_csr_rw |
115.360s |
117.040us |
0 |
1 |
0.00
|
| chip_jtag_mem_access |
0 |
1 |
0.00 |
|
chip_jtag_mem_access |
123.810s |
117.042us |
0 |
1 |
0.00
|
| chip_rv_dm_ndm_reset_req |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
252.060s |
272.275us |
1 |
1 |
100.00
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
11.313s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_access_after_wakeup |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_access_after_wakeup |
11.419s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_lc_disabled |
0 |
1 |
0.00 |
|
chip_rv_dm_lc_disabled |
80.440s |
125.525us |
0 |
1 |
0.00
|
| chip_sw_timer |
1 |
1 |
100.00 |
|
chip_sw_rv_timer_irq |
244.150s |
248.723us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wakeup_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
429.280s |
547.566us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_bark_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
429.280s |
547.566us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_lc_escalate |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_wdog_lc_escalate |
370.830s |
348.530us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.140s |
164.320us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.140s |
164.320us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_sleep_pause |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_sleep_wdog_sleep_pause |
299.520s |
2271.457us |
1 |
1 |
100.00
|
| chip_sw_plic_sw_irq |
1 |
1 |
100.00 |
|
chip_sw_plic_sw_irq |
149.220s |
145.514us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_idle_trans |
4 |
4 |
100.00 |
|
chip_sw_otbn_randomness |
254.550s |
225.630us |
1 |
1 |
100.00
|
|
chip_sw_aes_idle |
161.320s |
147.279us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_idle |
161.700s |
161.515us |
1 |
1 |
100.00
|
|
chip_sw_kmac_idle |
158.450s |
145.026us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_off_trans |
0 |
4 |
0.00 |
|
chip_sw_clkmgr_off_aes_trans |
176.640s |
165.648us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_hmac_trans |
170.930s |
165.664us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_kmac_trans |
174.450s |
165.632us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_otbn_trans |
172.930s |
165.632us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
37.110s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
39.100s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
41.650s |
10.320us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
36.430s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
36.350s |
10.380us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
10.120s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
157.230s |
141.843us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_extended_range |
1 |
8 |
12.50 |
|
chip_sw_clkmgr_jitter_reduced_freq |
300.900s |
1779.593us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
43.400s |
10.380us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
39.120s |
10.180us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
37.780s |
10.340us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq |
36.520s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
38.080s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
37.630s |
10.160us |
0 |
1 |
0.00
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
38.260s |
10.220us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_deep_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
10.534s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_sleep_frequency |
10.576s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_reset_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_reset_frequency |
22.299s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
902.170s |
905.674us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_external_full_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
346.540s |
495.394us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_sleep_all_reset_reqs |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.140s |
164.320us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_wdog_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_wdog_reset |
10.481s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_aon_power_glitch_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
346.540s |
495.394us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_main_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_main_power_glitch_reset |
12.617s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
9.436s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
9.359s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_power_glitch_reset |
9.423s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_disabled |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_disabled |
9.470s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
902.170s |
905.674us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sys_reset_info |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
252.060s |
272.275us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_cpu_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
374.980s |
375.168us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_req_reset |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_req |
255.590s |
267.317us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_alert_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
337.620s |
290.097us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_rst |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_rst |
153.600s |
144.146us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
902.170s |
905.674us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_test |
12.264s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_escalations |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
10.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_all_escalation_resets |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
902.170s |
905.674us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_entropy |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_entropy |
9.841s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_crashdump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
337.620s |
290.097us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_ping_timeout |
1 |
1 |
100.00 |
|
chip_sw_alert_handler_ping_timeout |
353.050s |
371.243us |
1 |
1 |
100.00
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_alerts |
10.646s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_sleep_mode_pings |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_pings |
10.486s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_clock_off |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_clkoff |
9.757s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_reset_toggle |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_reset_toggle |
9.703s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
10.083s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_alert_handler_escalation |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
10.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_jtag_access |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_otp_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
18.582s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_transitions |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_kmac_req |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_key_div |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation_prod |
278.930s |
267.716us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_broadcast |
2 |
10 |
20.00 |
|
chip_prim_tl_access |
365.320s |
621.074us |
1 |
1 |
100.00
|
|
chip_rv_dm_lc_disabled |
80.440s |
125.525us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
9.357s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
17.580s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
22.225s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
20.182s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation |
244.300s |
267.607us |
0 |
1 |
0.00
|
|
chip_sw_rom_ctrl_integrity_check |
735.870s |
1266.491us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_execution_main |
9.365s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_aes_enc |
1 |
2 |
50.00 |
|
chip_sw_aes_enc |
182.580s |
157.108us |
1 |
1 |
100.00
|
|
chip_sw_aes_enc_jitter_en |
39.100s |
10.240us |
0 |
1 |
0.00
|
| chip_sw_aes_entropy |
1 |
1 |
100.00 |
|
chip_sw_aes_entropy |
176.740s |
145.830us |
1 |
1 |
100.00
|
| chip_sw_aes_idle |
1 |
1 |
100.00 |
|
chip_sw_aes_idle |
161.320s |
147.279us |
1 |
1 |
100.00
|
| chip_sw_hmac_enc |
1 |
2 |
50.00 |
|
chip_sw_hmac_enc |
183.660s |
156.419us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_jitter_en |
41.650s |
10.320us |
0 |
1 |
0.00
|
| chip_sw_hmac_idle |
1 |
1 |
100.00 |
|
chip_sw_hmac_enc_idle |
161.700s |
161.515us |
1 |
1 |
100.00
|
| chip_sw_kmac_enc |
2 |
3 |
66.67 |
|
chip_sw_kmac_mode_cshake |
168.340s |
148.925us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac |
211.610s |
172.162us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
36.350s |
10.380us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_keymgr |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
244.300s |
267.607us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_lc |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_rom |
0 |
1 |
0.00 |
|
chip_sw_kmac_app_rom |
30.770s |
10.260us |
0 |
1 |
0.00
|
| chip_sw_kmac_entropy |
1 |
1 |
100.00 |
|
chip_sw_kmac_entropy |
238.920s |
187.962us |
1 |
1 |
100.00
|
| chip_sw_kmac_idle |
1 |
1 |
100.00 |
|
chip_sw_kmac_idle |
158.450s |
145.026us |
1 |
1 |
100.00
|
| chip_sw_entropy_src_csrng |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
363.450s |
273.506us |
1 |
1 |
100.00
|
| chip_sw_csrng_edn_cmd |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
363.450s |
273.506us |
1 |
1 |
100.00
|
| chip_sw_csrng_fuse_en_sw_app_read |
0 |
1 |
0.00 |
|
chip_sw_csrng_fuse_en_sw_app_read_test |
13.171s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_csrng_known_answer_tests |
1 |
1 |
100.00 |
|
chip_sw_csrng_kat_test |
185.550s |
156.798us |
1 |
1 |
100.00
|
| chip_sw_edn_entropy_reqs |
1 |
1 |
100.00 |
|
chip_sw_csrng_edn_concurrency |
1386.530s |
1212.648us |
1 |
1 |
100.00
|
| chip_sw_keymgr_dpe_key_derivation |
0 |
2 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
244.300s |
267.607us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
36.430s |
10.360us |
0 |
1 |
0.00
|
| chip_sw_otbn_op |
1 |
2 |
50.00 |
|
chip_sw_otbn_ecdsa_op_irq |
2315.320s |
1472.999us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
37.110s |
10.120us |
0 |
1 |
0.00
|
| chip_sw_otbn_rnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
254.550s |
225.630us |
1 |
1 |
100.00
|
| chip_sw_otbn_urnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
254.550s |
225.630us |
1 |
1 |
100.00
|
| chip_sw_otbn_idle |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
254.550s |
225.630us |
1 |
1 |
100.00
|
| chip_sw_otbn_mem_scramble |
1 |
1 |
100.00 |
|
chip_sw_otbn_mem_scramble |
373.290s |
264.668us |
1 |
1 |
100.00
|
| chip_sw_rom_access |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
735.870s |
1266.491us |
1 |
1 |
100.00
|
| chip_sw_rom_ctrl_integrity_check |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
735.870s |
1266.491us |
1 |
1 |
100.00
|
| chip_sw_sram_scrambled_access |
1 |
2 |
50.00 |
|
chip_sw_sram_ctrl_scrambled_access |
315.340s |
313.707us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
10.120s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_execution |
0 |
1 |
0.00 |
|
chip_sw_sram_ctrl_execution_main |
9.365s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_lc_escalation |
0 |
2 |
0.00 |
|
chip_sw_all_escalation_resets |
902.170s |
905.674us |
0 |
1 |
0.00
|
|
chip_sw_data_integrity_escalation |
147.900s |
0.000us |
0 |
1 |
0.00
|
| chip_otp_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_keys |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
373.290s |
264.668us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
244.300s |
267.607us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
315.340s |
313.707us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
165.930s |
156.647us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_entropy |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
373.290s |
264.668us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
244.300s |
267.607us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
315.340s |
313.707us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
165.930s |
156.647us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_program |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program_error |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_program_error |
9.443s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
18.582s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_lc_signals |
1 |
6 |
16.67 |
|
chip_prim_tl_access |
365.320s |
621.074us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
9.357s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
17.580s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
22.225s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
20.182s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
9.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_prim_tl_access |
1 |
1 |
100.00 |
|
chip_prim_tl_access |
365.320s |
621.074us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_nvm_cnt |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_nvm_cnt |
12.300s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_sw_parts |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_sw_parts |
10.548s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_clk_outputs |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
10.534s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_sys_clk_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
37.110s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
39.100s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
41.650s |
10.320us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
36.430s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
36.350s |
10.380us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
10.120s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
157.230s |
141.843us |
1 |
1 |
100.00
|
| chip_sw_soc_proxy_external_reset_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
158.590s |
143.360us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_irqs |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
158.590s |
143.360us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_wakeup_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_external_wakeup |
145.080s |
138.811us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_gpios |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_gpios |
145.950s |
136.473us |
0 |
1 |
0.00
|
| chip_sw_nmi_irq |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_nmi_irq |
335.140s |
251.582us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_rnd |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_rnd |
225.810s |
175.534us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_address_translation |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_address_translation |
189.530s |
164.765us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_icache_scrambled_access |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_icache_invalidate |
165.930s |
156.647us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_fault_dump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
374.980s |
375.168us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_double_fault |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
374.980s |
375.168us |
0 |
1 |
0.00
|
| chip_sw_smoketest |
14 |
14 |
100.00 |
|
chip_sw_aes_smoketest |
136.300s |
157.084us |
1 |
1 |
100.00
|
|
chip_sw_aon_timer_smoketest |
151.790s |
163.228us |
1 |
1 |
100.00
|
|
chip_sw_clkmgr_smoketest |
122.700s |
142.914us |
1 |
1 |
100.00
|
|
chip_sw_csrng_smoketest |
128.540s |
144.792us |
1 |
1 |
100.00
|
|
chip_sw_gpio_smoketest |
145.640s |
165.589us |
1 |
1 |
100.00
|
|
chip_sw_hmac_smoketest |
170.320s |
182.002us |
1 |
1 |
100.00
|
|
chip_sw_kmac_smoketest |
161.980s |
171.069us |
1 |
1 |
100.00
|
|
chip_sw_otbn_smoketest |
198.720s |
208.450us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_smoketest |
132.670s |
146.960us |
1 |
1 |
100.00
|
|
chip_sw_rv_plic_smoketest |
127.330s |
145.100us |
1 |
1 |
100.00
|
|
chip_sw_rv_timer_smoketest |
178.950s |
248.759us |
1 |
1 |
100.00
|
|
chip_sw_rstmgr_smoketest |
122.730s |
141.658us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_smoketest |
119.730s |
145.463us |
1 |
1 |
100.00
|
|
chip_sw_uart_smoketest |
137.400s |
155.788us |
1 |
1 |
100.00
|
| chip_sw_rom_functests |
0 |
1 |
0.00 |
|
rom_keymgr_functest |
9.512s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_signed |
0 |
1 |
0.00 |
|
chip_sw_uart_smoketest_signed |
10.725s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_boot |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
100.586s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_secure_boot |
0 |
1 |
0.00 |
|
base_rom_e2e_smoke |
11.111s |
0.000us |
0 |
1 |
0.00
|
| chip_lc_scrap |
4 |
4 |
100.00 |
|
chip_sw_lc_ctrl_rma_to_scrap |
178.260s |
198.499us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_raw_to_scrap |
173.320s |
225.917us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
181.980s |
215.954us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_rand_to_scrap |
179.520s |
191.984us |
1 |
1 |
100.00
|
| chip_lc_test_locked |
0 |
2 |
0.00 |
|
chip_rv_dm_lc_disabled |
80.440s |
125.525us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
12.278s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_walkthrough |
0 |
5 |
0.00 |
|
chip_sw_lc_walkthrough_dev |
33.775s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prod |
10.896s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prodend |
12.658s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_rma |
14.126s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
12.278s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_volatile_raw_unlock |
2 |
3 |
66.67 |
|
chip_sw_lc_ctrl_volatile_raw_unlock |
414.730s |
505.153us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
643.480s |
776.036us |
1 |
1 |
100.00
|
|
rom_volatile_raw_unlock |
10.342s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_raw_unlock |
0 |
1 |
0.00 |
|
rom_raw_unlock |
9.357s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_exit_test_unlocked_bootstrap |
0 |
1 |
0.00 |
|
chip_sw_exit_test_unlocked_bootstrap |
87.544s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_inject_scramble_seed |
0 |
1 |
0.00 |
|
chip_sw_inject_scramble_seed |
95.049s |
0.000us |
0 |
1 |
0.00
|
| tl_d_oob_addr_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
115.790s |
118.112us |
0 |
1 |
0.00
|
| tl_d_illegal_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
115.790s |
118.112us |
0 |
1 |
0.00
|
| tl_d_outstanding_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
9.700s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
8.800s |
0.000us |
0 |
1 |
0.00
|
| tl_d_partial_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
9.700s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
8.800s |
0.000us |
0 |
1 |
0.00
|
| xbar_base_random_sequence |
1 |
1 |
100.00 |
|
xbar_random |
105.120s |
277.386us |
1 |
1 |
100.00
|
| xbar_random_delay |
6 |
6 |
100.00 |
|
xbar_smoke_zero_delays |
8.810s |
12.222us |
1 |
1 |
100.00
|
|
xbar_smoke_large_delays |
297.650s |
2399.630us |
1 |
1 |
100.00
|
|
xbar_smoke_slow_rsp |
344.180s |
1990.678us |
1 |
1 |
100.00
|
|
xbar_random_zero_delays |
32.470s |
26.462us |
1 |
1 |
100.00
|
|
xbar_random_large_delays |
304.030s |
2449.969us |
1 |
1 |
100.00
|
|
xbar_random_slow_rsp |
910.710s |
5021.429us |
1 |
1 |
100.00
|
| xbar_unmapped_address |
2 |
2 |
100.00 |
|
xbar_unmapped_addr |
104.700s |
188.279us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
65.350s |
127.095us |
1 |
1 |
100.00
|
| xbar_error_cases |
2 |
2 |
100.00 |
|
xbar_error_random |
53.930s |
55.936us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
65.350s |
127.095us |
1 |
1 |
100.00
|
| xbar_all_access_same_device |
2 |
2 |
100.00 |
|
xbar_access_same_device |
83.400s |
199.032us |
1 |
1 |
100.00
|
|
xbar_access_same_device_slow_rsp |
2316.750s |
14314.519us |
1 |
1 |
100.00
|
| xbar_all_hosts_use_same_source_id |
1 |
1 |
100.00 |
|
xbar_same_source |
53.460s |
119.546us |
1 |
1 |
100.00
|
| xbar_stress_all |
2 |
2 |
100.00 |
|
xbar_stress_all |
1347.970s |
3397.668us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_error |
853.270s |
2066.537us |
1 |
1 |
100.00
|
| xbar_stress_with_reset |
2 |
2 |
100.00 |
|
xbar_stress_all_with_rand_reset |
1640.520s |
3110.833us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_reset_error |
2517.820s |
5786.136us |
1 |
1 |
100.00
|
| rom_e2e_smoke |
0 |
1 |
0.00 |
|
rom_e2e_smoke |
10.551s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_output |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_output |
10.849s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_exception_c |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_exception_c |
11.035s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_boot_policy_valid |
0 |
15 |
0.00 |
|
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
10.128s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
11.238s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
9.796s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
10.390s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
9.983s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
9.304s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
9.218s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
9.393s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
9.541s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
9.405s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
72.686s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
64.433s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
58.206s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
74.557s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
121.135s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_sigverify_always |
0 |
15 |
0.00 |
|
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
67.660s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
60.860s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
132.819s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
72.578s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
68.094s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
50.709s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
64.783s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
70.528s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
67.795s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
58.441s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
12.677s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
19.325s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
13.343s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
13.849s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
13.599s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_asm_init |
0 |
5 |
0.00 |
|
rom_e2e_asm_init_test_unlocked0 |
9.843s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_dev |
13.002s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod |
9.342s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod_end |
10.393s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_rma |
20.729s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_keymgr_init |
0 |
3 |
0.00 |
|
rom_e2e_keymgr_init_rom_ext_meas |
11.324s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
15.331s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
9.333s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_static_critical |
0 |
1 |
0.00 |
|
rom_e2e_static_critical |
12.798s |
0.000us |
0 |
1 |
0.00
|