Simulation Results: clkmgr

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.34 %
  • code
  • 69.38 %
  • assert
  • 88.64 %
  • func
  • 71.00 %
  • line
  • 82.19 %
  • branch
  • 87.58 %
  • cond
  • 77.51 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
25.00%
V2
47.37%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.890s 20.469us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.800s 30.891us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.310s 196.714us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.970s 47.935us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.590s 5.458us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
clkmgr_csr_aliasing 0.970s 47.935us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.710s 16.117us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.120s 72.789us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.640s 13.566us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.890s 20.469us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.690s 7.703us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.640s 9.667us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.690s 7.703us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.920s 34.307us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 17.666us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.130s 114.349us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.130s 114.349us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.800s 30.891us 1 1 100.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
clkmgr_csr_aliasing 0.970s 47.935us 0 1 0.00
clkmgr_same_csr_outstanding 0.660s 14.436us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.800s 30.891us 1 1 100.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
clkmgr_csr_aliasing 0.970s 47.935us 0 1 0.00
clkmgr_same_csr_outstanding 0.660s 14.436us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.760s 789.652us 1 1 100.00
clkmgr_tl_intg_err 1.050s 62.391us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 46.418us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 46.418us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 46.418us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 46.418us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.660s 5.311us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.050s 62.391us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.690s 7.703us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.640s 9.667us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 46.418us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.410s 101.608us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.760s 789.652us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.580s 4.852us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.760s 789.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 3.909us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.660s 7.029us 0 1 0.00