Simulation Results: dma

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 81.67 %
  • code
  • 90.06 %
  • assert
  • 95.97 %
  • func
  • 58.98 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 84.51 %
Validation stages
V1
100.00%
V2
95.24%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 318.110us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 576.404us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 451.753us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 29.018us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 27.313us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 10.000s 309.347us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 902.168us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 30.674us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 27.313us 1 1 100.00
dma_csr_aliasing 5.000s 902.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 36.000s 5893.140us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 233.000s 34999.184us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 514.000s 51154.954us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 514.000s 51154.954us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 233.000s 34999.184us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 162.000s 16783.979us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 514.000s 51154.954us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 775.825us 1 1 100.00
dma_stress_all 0 1 0.00
dma_stress_all 81.000s 26110.448us 0 1 0.00
alert_test 1 1 100.00
dma_alert_test 2.000s 115.898us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 44.381us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 71.216us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 71.216us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 29.018us 1 1 100.00
dma_csr_rw 2.000s 27.313us 1 1 100.00
dma_csr_aliasing 5.000s 902.168us 1 1 100.00
dma_same_csr_outstanding 3.000s 392.230us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 29.018us 1 1 100.00
dma_csr_rw 2.000s 27.313us 1 1 100.00
dma_csr_aliasing 5.000s 902.168us 1 1 100.00
dma_same_csr_outstanding 3.000s 392.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 15.000s 812.780us 1 1 100.00
dma_generic_stress 162.000s 16783.979us 1 1 100.00
dma_handshake_stress 514.000s 51154.954us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1420.351us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 11.216us 1 1 100.00
dma_tl_intg_err 2.000s 415.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 86.000s 11086.748us 1 1 100.00
dma_longer_transfer 12.000s 449.209us 1 1 100.00
dma_stress_all_with_rand_reset 8.000s 2459.670us 0 1 0.00