Simulation Results: edn

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.21 %
  • code
  • 81.88 %
  • assert
  • 95.11 %
  • func
  • 78.63 %
  • line
  • 97.51 %
  • branch
  • 91.94 %
  • cond
  • 87.92 %
  • toggle
  • 82.61 %
  • FSM
  • 49.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 40.179us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 19.090us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 51.864us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.150s 1808.898us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.900s 40.087us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.280s 30.956us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 51.864us 1 1 100.00
edn_csr_aliasing 0.900s 40.087us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 59.166us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 59.166us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 59.166us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 22.455us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 26.120us 1 1 100.00
errs 1 1 100.00
edn_err 0.850s 21.900us 1 1 100.00
disable 2 2 100.00
edn_disable 0.970s 13.932us 1 1 100.00
edn_disable_auto_req_mode 0.970s 78.634us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.440s 493.152us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 22.907us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 60.885us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.450s 174.757us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.450s 174.757us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.090us 1 1 100.00
edn_csr_rw 0.830s 51.864us 1 1 100.00
edn_csr_aliasing 0.900s 40.087us 1 1 100.00
edn_same_csr_outstanding 0.950s 112.937us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.090us 1 1 100.00
edn_csr_rw 0.830s 51.864us 1 1 100.00
edn_csr_aliasing 0.900s 40.087us 1 1 100.00
edn_same_csr_outstanding 0.950s 112.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.230s 2499.356us 1 1 100.00
edn_tl_intg_err 1.300s 209.870us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 25.161us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 26.120us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.230s 2499.356us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.230s 2499.356us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.230s 2499.356us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.230s 2499.356us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 26.120us 1 1 100.00
edn_sec_cm 7.230s 2499.356us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 26.120us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.300s 209.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.980s 4890.122us 1 1 100.00