Simulation Results: hmac

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.34 %
  • code
  • 97.09 %
  • assert
  • 96.42 %
  • func
  • 44.50 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.630s 1354.544us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.840s 42.636us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.860s 35.339us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.940s 1229.764us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.130s 2728.969us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.850s 28.599us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.860s 35.339us 1 1 100.00
hmac_csr_aliasing 6.130s 2728.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 41.450s 6288.692us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 74.550s 6938.085us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.040s 2072.300us 1 1 100.00
hmac_test_sha384_vectors 325.400s 79964.467us 1 1 100.00
hmac_test_sha512_vectors 21.230s 1157.045us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 2532.771us 1 1 100.00
hmac_test_hmac384_vectors 9.300s 1050.708us 1 1 100.00
hmac_test_hmac512_vectors 8.780s 258.465us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.020s 2392.892us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 710.380s 10658.924us 1 1 100.00
error 1 1 100.00
hmac_error 28.770s 3296.120us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 59.970s 1642.366us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.630s 1354.544us 1 1 100.00
hmac_long_msg 41.450s 6288.692us 1 1 100.00
hmac_back_pressure 74.550s 6938.085us 1 1 100.00
hmac_datapath_stress 710.380s 10658.924us 1 1 100.00
hmac_burst_wr 5.020s 2392.892us 1 1 100.00
hmac_stress_all 159.310s 11732.682us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.630s 1354.544us 1 1 100.00
hmac_long_msg 41.450s 6288.692us 1 1 100.00
hmac_back_pressure 74.550s 6938.085us 1 1 100.00
hmac_datapath_stress 710.380s 10658.924us 1 1 100.00
hmac_wipe_secret 59.970s 1642.366us 1 1 100.00
hmac_test_sha256_vectors 8.040s 2072.300us 1 1 100.00
hmac_test_sha384_vectors 325.400s 79964.467us 1 1 100.00
hmac_test_sha512_vectors 21.230s 1157.045us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 2532.771us 1 1 100.00
hmac_test_hmac384_vectors 9.300s 1050.708us 1 1 100.00
hmac_test_hmac512_vectors 8.780s 258.465us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.630s 1354.544us 1 1 100.00
hmac_long_msg 41.450s 6288.692us 1 1 100.00
hmac_back_pressure 74.550s 6938.085us 1 1 100.00
hmac_datapath_stress 710.380s 10658.924us 1 1 100.00
hmac_burst_wr 5.020s 2392.892us 1 1 100.00
hmac_error 28.770s 3296.120us 1 1 100.00
hmac_wipe_secret 59.970s 1642.366us 1 1 100.00
hmac_test_sha256_vectors 8.040s 2072.300us 1 1 100.00
hmac_test_sha384_vectors 325.400s 79964.467us 1 1 100.00
hmac_test_sha512_vectors 21.230s 1157.045us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 2532.771us 1 1 100.00
hmac_test_hmac384_vectors 9.300s 1050.708us 1 1 100.00
hmac_test_hmac512_vectors 8.780s 258.465us 1 1 100.00
hmac_stress_all 159.310s 11732.682us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 159.310s 11732.682us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.610s 38.407us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 64.551us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 577.635us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 577.635us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.840s 42.636us 1 1 100.00
hmac_csr_rw 0.860s 35.339us 1 1 100.00
hmac_csr_aliasing 6.130s 2728.969us 1 1 100.00
hmac_same_csr_outstanding 1.790s 81.289us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.840s 42.636us 1 1 100.00
hmac_csr_rw 0.860s 35.339us 1 1 100.00
hmac_csr_aliasing 6.130s 2728.969us 1 1 100.00
hmac_same_csr_outstanding 1.790s 81.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 1.430s 183.554us 1 1 100.00
hmac_sec_cm 0.820s 258.117us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.430s 183.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.630s 1354.544us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.760s 232.089us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 24.930s 3052.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.090s 74.758us 1 1 100.00