| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
0.920s |
20.157us |
0 |
1 |
0.00
|
| host_stress_all |
0 |
1 |
0.00 |
|
i2c_host_stress_all |
591.680s |
25425.028us |
0 |
1 |
0.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
78.090s |
2680.307us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.740s |
43.542us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
88.240s |
11485.094us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
42.140s |
8826.899us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
1.500s |
173.909us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
13.950s |
400.117us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
5.750s |
272.302us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
35.150s |
2028.908us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
12.930s |
1811.342us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
1 |
1 |
100.00 |
|
i2c_host_mode_toggle |
1.600s |
95.628us |
1 |
1 |
100.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
3.810s |
462.904us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
48.340s |
19531.283us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
4.790s |
807.932us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
4.190s |
494.544us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
3.890s |
8731.533us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
1.040s |
492.563us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.700s |
206.966us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
151.260s |
64603.051us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
4.190s |
494.544us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
27.560s |
19479.600us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
6.930s |
1315.607us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
54.670s |
1918.268us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
2.450s |
523.235us |
1 |
1 |
100.00
|
| target_mode_glitch |
1 |
1 |
100.00 |
|
i2c_target_hrst |
1.140s |
274.069us |
1 |
1 |
100.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
3.540s |
2446.687us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.060s |
238.760us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
78.090s |
2680.307us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
3.600s |
447.014us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
12.930s |
1811.342us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
0 |
1 |
0.00 |
|
i2c_target_tx_stretch_ctrl |
1.090s |
26.596us |
0 |
1 |
0.00
|
| target_mode_nack_generation |
3 |
3 |
100.00 |
|
i2c_target_nack_acqfull |
2.980s |
2408.934us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
2.880s |
983.293us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.230s |
275.128us |
1 |
1 |
100.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
9.300s |
1147.082us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
2.630s |
612.483us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.770s |
23.798us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.970s |
15.787us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.380s |
40.193us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.380s |
40.193us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.760s |
92.033us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.710s |
43.931us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.510s |
62.942us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
0.960s |
50.910us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.760s |
92.033us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.710s |
43.931us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.510s |
62.942us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
0.960s |
50.910us |
1 |
1 |
100.00
|