Simulation Results: lc_ctrl

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.19 %
  • code
  • 88.78 %
  • assert
  • 95.99 %
  • func
  • 85.79 %
  • line
  • 97.64 %
  • branch
  • 96.13 %
  • cond
  • 79.59 %
  • toggle
  • 82.43 %
  • FSM
  • 88.10 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.200s 112.710us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 17.935us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 43.664us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.030s 106.606us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 43.142us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.330s 23.065us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 43.664us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 43.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.250s 5.318us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.710s 256.208us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.860s 36.687us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.480s 107.579us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.990s 271.119us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_prog_failure 1.480s 107.579us 1 1 100.00
lc_ctrl_errors 4.990s 271.119us 1 1 100.00
lc_ctrl_security_escalation 4.350s 279.855us 1 1 100.00
lc_ctrl_jtag_state_failure 3.850s 574.279us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.980s 236.863us 1 1 100.00
lc_ctrl_jtag_errors 22.360s 2994.115us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.140s 443.343us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.220s 694.531us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.760s 1515.098us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.190s 244.360us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 125.549us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.750s 170.067us 1 1 100.00
lc_ctrl_jtag_alert_test 1.620s 1190.720us 1 1 100.00
lc_ctrl_jtag_smoke 2.040s 171.391us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.280s 800.677us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.980s 236.863us 1 1 100.00
lc_ctrl_jtag_errors 22.360s 2994.115us 1 1 100.00
lc_ctrl_jtag_access 2.600s 280.497us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.800s 1015.072us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.240s 155.411us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.960s 16.239us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 15.360s 1006.926us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.820s 290.560us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.300s 60.405us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.300s 60.405us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 17.935us 1 1 100.00
lc_ctrl_csr_rw 0.850s 43.664us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 43.142us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.800s 84.490us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 17.935us 1 1 100.00
lc_ctrl_csr_rw 0.850s 43.664us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 43.142us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.800s 84.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.900s 261.702us 1 1 100.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.900s 261.702us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.710s 256.208us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.000s 62.859us 0 1 0.00
lc_ctrl_sec_cm 5.570s 834.460us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.350s 279.855us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.250s 5.318us 0 1 0.00
lc_ctrl_jtag_state_post_trans 6.280s 800.677us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.580s 416.293us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.580s 416.293us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.180s 1541.213us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.060s 669.020us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.060s 669.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.420s 959.710us 0 1 0.00