Simulation Results: lc_ctrl

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.06 %
  • code
  • 86.53 %
  • assert
  • 95.99 %
  • func
  • 90.65 %
  • line
  • 97.71 %
  • branch
  • 96.01 %
  • cond
  • 79.47 %
  • toggle
  • 82.72 %
  • FSM
  • 76.74 %
Validation stages
V1
100.00%
V2
90.00%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.170s 36.691us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.820s 31.027us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.750s 53.983us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.340s 361.100us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 20.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 25.175us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.750s 53.983us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 20.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.480s 79.151us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.890s 365.335us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 14.390us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.140s 20.088us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.430s 337.311us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_prog_failure 1.140s 20.088us 1 1 100.00
lc_ctrl_errors 7.430s 337.311us 1 1 100.00
lc_ctrl_security_escalation 5.990s 1898.378us 1 1 100.00
lc_ctrl_jtag_state_failure 8.640s 3968.333us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.410s 223.925us 1 1 100.00
lc_ctrl_jtag_errors 11.830s 8183.535us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.530s 54.490us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.900s 483.919us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.370s 461.557us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.620s 955.164us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.920s 217.433us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.120s 280.484us 1 1 100.00
lc_ctrl_jtag_alert_test 2.440s 656.701us 1 1 100.00
lc_ctrl_jtag_smoke 8.260s 1101.909us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.260s 475.828us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.410s 223.925us 1 1 100.00
lc_ctrl_jtag_errors 11.830s 8183.535us 1 1 100.00
lc_ctrl_jtag_access 5.010s 2518.808us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.260s 936.575us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.020s 181.653us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.890s 87.892us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 23.810s 2211.313us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.940s 70.417us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 54.293us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 54.293us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 31.027us 1 1 100.00
lc_ctrl_csr_rw 0.750s 53.983us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 20.084us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 40.558us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 31.027us 1 1 100.00
lc_ctrl_csr_rw 0.750s 53.983us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 20.084us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 40.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.230s 87.078us 1 1 100.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 87.078us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.890s 365.335us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.280s 325.367us 0 1 0.00
lc_ctrl_sec_cm 6.140s 247.419us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.990s 1898.378us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 4.480s 79.151us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.260s 475.828us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.170s 661.230us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.170s 661.230us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.320s 1350.587us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.500s 2052.966us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.500s 2052.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.950s 1465.200us 0 1 0.00