| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 56.000s | 9732.715us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 45.137us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 17.480us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 255.749us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 17.937us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 43.627us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 17.480us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 17.937us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 106.000s | 18058.280us | 1 | 1 | 100.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 2.000s | 71.144us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 60.000s | 21656.869us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 18.000s | 3554.261us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 31.493us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 1.000s | 15.226us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 3.000s | 125.708us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 3.000s | 125.708us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 45.137us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 17.480us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 17.937us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 75.504us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 45.137us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 17.480us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 17.937us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 75.504us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 2.000s | 35.887us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 2.000s | 83.064us | 1 | 1 | 100.00 | |