Simulation Results: rom_ctrl

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.35 %
  • code
  • 92.00 %
  • assert
  • 95.34 %
  • func
  • 95.70 %
  • line
  • 99.46 %
  • branch
  • 97.45 %
  • cond
  • 90.34 %
  • toggle
  • 99.44 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
33.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.340s 398.480us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.690s 542.375us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.310s 173.993us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.870s 168.807us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.930s 1690.975us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.550s 178.103us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.310s 173.993us 1 1 100.00
rom_ctrl_csr_aliasing 2.930s 1690.975us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.540s 134.340us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.560s 125.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.800s 189.874us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.700s 1202.059us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 2076.387us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.550s 868.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.250s 347.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.250s 347.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.690s 542.375us 1 1 100.00
rom_ctrl_csr_rw 4.310s 173.993us 1 1 100.00
rom_ctrl_csr_aliasing 2.930s 1690.975us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.610s 2743.760us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.690s 542.375us 1 1 100.00
rom_ctrl_csr_rw 4.310s 173.993us 1 1 100.00
rom_ctrl_csr_aliasing 2.930s 1690.975us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.610s 2743.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.380s 829.947us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 101.360s 624.914us 0 1 0.00
rom_ctrl_tl_intg_err 41.900s 1094.029us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 101.360s 624.914us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 101.360s 624.914us 0 1 0.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 101.360s 624.914us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 101.360s 624.914us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.340s 398.480us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.340s 398.480us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.340s 398.480us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.900s 1094.029us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
rom_ctrl_kmac_err_chk 10.000s 2076.387us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 21.110s 6407.634us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.380s 829.947us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 101.360s 624.914us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 81.510s 13727.416us 1 1 100.00