Simulation Results: rom_ctrl

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.82 %
  • code
  • 98.30 %
  • assert
  • 95.49 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 94.21 %
  • toggle
  • 99.31 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.650s 1469.612us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.960s 1031.447us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.720s 385.365us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.690s 698.766us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.700s 216.711us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.600s 529.776us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.720s 385.365us 1 1 100.00
rom_ctrl_csr_aliasing 6.700s 216.711us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.690s 1064.222us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.600s 1413.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.650s 571.269us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.330s 599.778us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.580s 1346.500us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.350s 234.661us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 11.070s 1689.217us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 11.070s 1689.217us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.960s 1031.447us 1 1 100.00
rom_ctrl_csr_rw 6.720s 385.365us 1 1 100.00
rom_ctrl_csr_aliasing 6.700s 216.711us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.540s 1213.977us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.960s 1031.447us 1 1 100.00
rom_ctrl_csr_rw 6.720s 385.365us 1 1 100.00
rom_ctrl_csr_aliasing 6.700s 216.711us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.540s 1213.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.440s 1572.460us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_tl_intg_err 99.430s 438.866us 1 1 100.00
rom_ctrl_sec_cm 447.840s 9979.171us 0 1 0.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 447.840s 9979.171us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 447.840s 9979.171us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 447.840s 9979.171us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 447.840s 9979.171us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.650s 1469.612us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.650s 1469.612us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.650s 1469.612us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 99.430s 438.866us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
rom_ctrl_kmac_err_chk 14.580s 1346.500us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 156.490s 9687.446us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.440s 1572.460us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 447.840s 9979.171us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 116.860s 17729.179us 1 1 100.00