Simulation Results: rstmgr

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.35 %
  • code
  • 99.32 %
  • assert
  • 97.25 %
  • func
  • 95.48 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.030s 63.311us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.900s 63.969us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.770s 37.131us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.200s 106.499us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.960s 38.079us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.210s 69.397us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.770s 37.131us 1 1 100.00
rstmgr_csr_aliasing 0.960s 38.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.320s 188.668us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.880s 42.716us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.040s 92.535us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.550s 572.412us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.550s 572.412us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.550s 572.412us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.550s 572.412us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.810s 863.281us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 43.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.610s 45.861us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.610s 45.861us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.900s 63.969us 1 1 100.00
rstmgr_csr_rw 0.770s 37.131us 1 1 100.00
rstmgr_csr_aliasing 0.960s 38.079us 1 1 100.00
rstmgr_same_csr_outstanding 1.020s 66.236us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.900s 63.969us 1 1 100.00
rstmgr_csr_rw 0.770s 37.131us 1 1 100.00
rstmgr_csr_aliasing 0.960s 38.079us 1 1 100.00
rstmgr_same_csr_outstanding 1.020s 66.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.900s 3503.862us 1 1 100.00
rstmgr_tl_intg_err 2.180s 329.142us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.900s 3503.862us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.900s 3503.862us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.180s 329.142us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.010s 59.513us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.390s 466.109us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.020s 291.314us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.900s 3503.862us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.770s 37.131us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.770s 37.131us 1 1 100.00