Simulation Results: rv_dm

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.70 %
  • code
  • 71.42 %
  • assert
  • 96.24 %
  • func
  • 71.43 %
  • line
  • 90.11 %
  • branch
  • 74.36 %
  • cond
  • 72.98 %
  • toggle
  • 69.64 %
  • FSM
  • 50.00 %
Validation stages
V1
93.55%
V2
60.71%
V2S
83.33%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 2.680s 3440.438us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.450s 405.899us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.850s 282.381us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 47.950s 27633.568us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 0.770s 693.269us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 4.130s 5210.240us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 1.230s 1150.752us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 39.750s 89254.885us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 34.970s 81571.238us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 0.810s 1252.462us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.750s 167.325us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.290s 791.011us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.730s 308.978us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.650s 105.535us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 0.940s 304.957us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.680s 121.156us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 0.960s 582.644us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 0.810s 1252.462us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.010s 446.901us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 0.910s 1077.671us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.290s 791.011us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.870s 168.177us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.350s 303.492us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.740s 151.184us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 21.140s 2570.688us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 48.060s 4162.081us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.680s 27.108us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 48.060s 4162.081us 1 1 100.00
rv_dm_csr_rw 1.740s 151.184us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.680s 92.871us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.610s 47.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 2.680s 3440.438us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.940s 218.587us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.760s 147.264us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.310s 387.629us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.360s 840.123us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 295.960s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 186.420s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 598.370s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 259.310s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.730s 101.251us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 2.100s 3898.620us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.930s 660.327us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.640s 67.722us 0 1 0.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm_rand_reset 0.640s 26.151us 0 1 0.00
rv_dm_tap_fsm 11.610s 11626.311us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.850s 83.461us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.670s 110.968us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 0.730s 38.288us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 0.730s 38.288us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 48.060s 4162.081us 1 1 100.00
rv_dm_csr_hw_reset 1.350s 303.492us 1 1 100.00
rv_dm_csr_rw 1.740s 151.184us 1 1 100.00
rv_dm_same_csr_outstanding 5.250s 562.328us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 48.060s 4162.081us 1 1 100.00
rv_dm_csr_hw_reset 1.350s 303.492us 1 1 100.00
rv_dm_csr_rw 1.740s 151.184us 1 1 100.00
rv_dm_same_csr_outstanding 5.250s 562.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 7.850s 1597.827us 1 1 100.00
rv_dm_sec_cm 1.150s 912.525us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 7.850s 1597.827us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.100s 3898.620us 1 1 100.00
rv_dm_debug_disabled 0.860s 114.874us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.100s 3898.620us 1 1 100.00
rv_dm_debug_disabled 0.860s 114.874us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 2.680s 3440.438us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 0.830s 185.808us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.760s 94.828us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.760s 94.828us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 0.830s 185.808us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.830s 189.481us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 560.430s 300000.000us 0 1 0.00