| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
33.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 1.020s | 873.656us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.670s | 11.739us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.550s | 35.022us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.980s | 375.132us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.690s | 38.352us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.710s | 44.083us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 0.550s | 35.022us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.690s | 38.352us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.800s | 350.625us | 0 | 1 | 0.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 1.390s | 710.680us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 9.120s | 37418.684us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 9.120s | 37418.684us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 2.850s | 3081.815us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 0.580s | 32.658us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.620s | 14.584us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 2.510s | 647.229us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 2.510s | 647.229us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.670s | 11.739us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.550s | 35.022us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.690s | 38.352us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.720s | 18.029us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.670s | 11.739us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.550s | 35.022us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.690s | 38.352us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.720s | 18.029us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 1.090s | 619.811us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 1.040s | 83.651us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 1.040s | 83.651us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 1 | 0.00 | |||
| rv_timer_min | 8.990s | 1862.699us | 0 | 1 | 0.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.820s | 162.936us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_stress_all_with_rand_reset | 4.240s | 3952.589us | 1 | 1 | 100.00 | |