Simulation Results: spi_device

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.76 %
  • code
  • 93.07 %
  • assert
  • 94.30 %
  • func
  • 72.92 %
  • line
  • 99.03 %
  • branch
  • 98.21 %
  • cond
  • 95.56 %
  • toggle
  • 83.19 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 122.070s 63388.944us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.970s 29.197us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.520s 67.876us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 7.670s 745.311us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.260s 4393.538us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.460s 55.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.520s 67.876us 1 1 100.00
spi_device_csr_aliasing 5.260s 4393.538us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.650s 34.243us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.140s 38.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.820s 35.362us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.780s 3.014us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.820s 3.907us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.760s 140.388us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.760s 140.388us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.420s 7152.053us 1 1 100.00
spi_device_tpm_sts_read 0.860s 26.167us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 14.140s 15567.196us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.660s 84.440us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.720s 111.450us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.720s 111.450us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.890s 106.769us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.890s 106.769us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.890s 106.769us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.890s 106.769us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.890s 106.769us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.590s 797.892us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.460s 30932.218us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.460s 30932.218us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.460s 30932.218us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.620s 1929.626us 1 1 100.00
spi_device_read_buffer_direct 8.850s 5821.113us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.460s 30932.218us 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 93.630s 133101.694us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 10.020s 1575.236us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 10.020s 1575.236us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 122.070s 63388.944us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 22.680s 9102.991us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 75.190s 19532.583us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.840s 15.538us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 22.422us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.510s 960.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.510s 960.755us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 29.197us 1 1 100.00
spi_device_csr_rw 1.520s 67.876us 1 1 100.00
spi_device_csr_aliasing 5.260s 4393.538us 1 1 100.00
spi_device_same_csr_outstanding 2.750s 237.459us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 29.197us 1 1 100.00
spi_device_csr_rw 1.520s 67.876us 1 1 100.00
spi_device_csr_aliasing 5.260s 4393.538us 1 1 100.00
spi_device_same_csr_outstanding 2.750s 237.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 8.710s 800.734us 1 1 100.00
spi_device_sec_cm 1.070s 425.619us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.710s 800.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 84.860s 188122.095us 1 1 100.00