Simulation Results: sram_ctrl

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.68 %
  • code
  • 88.24 %
  • assert
  • 95.55 %
  • func
  • 94.25 %
  • line
  • 97.32 %
  • branch
  • 95.05 %
  • cond
  • 91.43 %
  • toggle
  • 90.71 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 23.900s 2893.862us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.780s 47.273us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 53.708us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.250s 73.760us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.960s 13.459us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.200s 361.399us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 53.708us 1 1 100.00
sram_ctrl_csr_aliasing 0.960s 13.459us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 115.780s 15703.475us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 47.010s 970.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 502.790s 86848.538us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 263.090s 53952.072us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 948.080s 221582.291us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 64.940s 1514.162us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 14.260s 44803.253us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 202.560s 75222.440us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.710s 967.218us 1 1 100.00
sram_ctrl_partial_access_b2b 345.570s 32888.705us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 41.210s 3920.582us 1 1 100.00
sram_ctrl_throughput_w_partial_write 10.620s 2777.710us 1 1 100.00
sram_ctrl_throughput_w_readback 30.410s 1760.173us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 405.700s 10767.667us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.910s 1245.696us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2611.090s 155488.465us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.760s 16.346us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.080s 45.878us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.080s 45.878us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 47.273us 1 1 100.00
sram_ctrl_csr_rw 0.710s 53.708us 1 1 100.00
sram_ctrl_csr_aliasing 0.960s 13.459us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.780s 20.979us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 47.273us 1 1 100.00
sram_ctrl_csr_rw 0.710s 53.708us 1 1 100.00
sram_ctrl_csr_aliasing 0.960s 13.459us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.780s 20.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.040s 7411.417us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.830s 543.016us 1 1 100.00
sram_ctrl_sec_cm 1.020s 8.088us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 1.020s 8.088us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.830s 543.016us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 405.700s 10767.667us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 405.700s 10767.667us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 53.708us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 202.560s 75222.440us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 202.560s 75222.440us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 202.560s 75222.440us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 14.260s 44803.253us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.260s 1406.765us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.040s 7411.417us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.040s 683.017us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 23.900s 2893.862us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 23.900s 2893.862us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 202.560s 75222.440us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 1.020s 8.088us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 14.260s 44803.253us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 1.020s 8.088us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.020s 8.088us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 23.900s 2893.862us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.020s 8.088us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 5.170s 431.958us 1 1 100.00