Simulation Results: sram_ctrl

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.50 %
  • code
  • 88.99 %
  • assert
  • 95.79 %
  • func
  • 95.73 %
  • line
  • 97.12 %
  • branch
  • 93.94 %
  • cond
  • 91.80 %
  • toggle
  • 90.66 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 14.810s 6769.625us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.680s 55.775us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.620s 17.133us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.620s 173.512us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 63.965us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.920s 42.619us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.620s 17.133us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 63.965us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.600s 274.286us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.460s 91.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 445.030s 10861.944us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 197.510s 3102.236us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 29.710s 1204.920us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 870.930s 20856.607us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.220s 271.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 423.420s 93681.749us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.140s 1163.792us 1 1 100.00
sram_ctrl_partial_access_b2b 366.800s 121829.868us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 37.210s 103.894us 1 1 100.00
sram_ctrl_throughput_w_partial_write 12.780s 386.774us 1 1 100.00
sram_ctrl_throughput_w_readback 52.980s 1097.390us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 24.560s 1904.466us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.020s 49.781us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1863.090s 12251.019us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.750s 15.308us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.900s 75.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.900s 75.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.680s 55.775us 1 1 100.00
sram_ctrl_csr_rw 0.620s 17.133us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 63.965us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.690s 15.969us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.680s 55.775us 1 1 100.00
sram_ctrl_csr_rw 0.620s 17.133us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 63.965us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.690s 15.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.600s 734.442us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.350s 1392.030us 1 1 100.00
sram_ctrl_sec_cm 0.880s 4.269us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.880s 4.269us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.350s 1392.030us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 24.560s 1904.466us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 24.560s 1904.466us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.620s 17.133us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 423.420s 93681.749us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 423.420s 93681.749us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 423.420s 93681.749us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.220s 271.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 1.270s 227.828us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.600s 734.442us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 175.326us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 14.810s 6769.625us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 14.810s 6769.625us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 423.420s 93681.749us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.880s 4.269us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.220s 271.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.880s 4.269us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.880s 4.269us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 14.810s 6769.625us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.880s 4.269us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 181.480s 6470.499us 1 1 100.00