Simulation Results: uart

 
02/12/2025 16:09:27 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.00 %
  • code
  • 95.52 %
  • assert
  • 97.12 %
  • func
  • 50.35 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 94.40 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.560s 655.157us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.560s 59.720us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.640s 76.497us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.250s 38.641us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.680s 32.644us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 31.345us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.640s 76.497us 1 1 100.00
uart_csr_aliasing 0.680s 32.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 32.830s 27401.081us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.560s 655.157us 1 1 100.00
uart_tx_rx 32.830s 27401.081us 1 1 100.00
parity_error 2 2 100.00
uart_intr 23.940s 77046.350us 1 1 100.00
uart_rx_parity_err 9.370s 21673.344us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 32.830s 27401.081us 1 1 100.00
uart_intr 23.940s 77046.350us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 48.060s 163558.091us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 8.440s 26590.029us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 37.940s 31530.496us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 23.940s 77046.350us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 23.940s 77046.350us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 23.940s 77046.350us 1 1 100.00
perf 1 1 100.00
uart_perf 321.890s 8310.238us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.030s 247.283us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.030s 247.283us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.970s 2467.515us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.860s 3121.337us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 13.840s 7251.084us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.710s 6782.659us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 225.150s 186871.748us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 17.160s 26253.411us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.620s 30.677us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 50.934us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.070s 49.037us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.070s 49.037us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.560s 59.720us 1 1 100.00
uart_csr_rw 0.640s 76.497us 1 1 100.00
uart_csr_aliasing 0.680s 32.644us 1 1 100.00
uart_same_csr_outstanding 0.700s 163.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.560s 59.720us 1 1 100.00
uart_csr_rw 0.640s 76.497us 1 1 100.00
uart_csr_aliasing 0.680s 32.644us 1 1 100.00
uart_same_csr_outstanding 0.700s 163.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.940s 73.613us 1 1 100.00
uart_tl_intg_err 1.130s 121.706us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.130s 121.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 1.460s 405.019us 0 1 0.00