Simulation Results: ac_range_check

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.75 %
  • code
  • 92.92 %
  • assert
  • 97.63 %
  • func
  • 57.70 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 80.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 30.000s 1275.864us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 50.000s 12070.820us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 36.052us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 41.599us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 30.000s 6562.829us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 22.000s 5657.874us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 34.750us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 41.599us 1 1 100.00
ac_range_check_csr_aliasing 22.000s 5657.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 4.000s 82.120us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 44.000s 4613.372us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 70.000s 5920.708us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 45.085us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 3.000s 87.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 54.133us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 54.133us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 36.052us 1 1 100.00
ac_range_check_csr_rw 3.000s 41.599us 1 1 100.00
ac_range_check_csr_aliasing 22.000s 5657.874us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 140.295us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 36.052us 1 1 100.00
ac_range_check_csr_rw 3.000s 41.599us 1 1 100.00
ac_range_check_csr_aliasing 22.000s 5657.874us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 140.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 4340.175us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 4340.175us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 4340.175us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 4340.175us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 81.000s 17458.180us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 36.929us 1 1 100.00
ac_range_check_tl_intg_err 10.000s 119.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 204.000s 9614.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 23.000s 788.369us 1 1 100.00