Simulation Results: clkmgr

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.19 %
  • code
  • 69.34 %
  • assert
  • 88.43 %
  • func
  • 61.79 %
  • line
  • 82.19 %
  • branch
  • 87.58 %
  • cond
  • 77.85 %
  • toggle
  • 99.06 %
  • FSM
  • 0.00 %
Validation stages
V1
25.00%
V2
47.37%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.010s 15.770us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.880s 24.031us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.360s 42.098us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.720s 5.722us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.820s 6.082us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
clkmgr_csr_aliasing 0.720s 5.722us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.890s 23.225us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.370s 35.319us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.050s 32.391us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.010s 15.770us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.740s 15.157us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.790s 4.140us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.740s 15.157us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.390s 64.418us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.000s 47.441us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.430s 27.806us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.430s 27.806us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.880s 24.031us 1 1 100.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
clkmgr_csr_aliasing 0.720s 5.722us 0 1 0.00
clkmgr_same_csr_outstanding 0.590s 3.226us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.880s 24.031us 1 1 100.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
clkmgr_csr_aliasing 0.720s 5.722us 0 1 0.00
clkmgr_same_csr_outstanding 0.590s 3.226us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.820s 298.962us 1 1 100.00
clkmgr_tl_intg_err 0.730s 2.062us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 49.117us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 49.117us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 49.117us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 49.117us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.650s 2.264us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.730s 2.062us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.740s 15.157us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.790s 4.140us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 49.117us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.730s 109.270us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.820s 298.962us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 3.701us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.820s 298.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.710s 3.161us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.820s 64.120us 0 1 0.00