Simulation Results: dma

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.11 %
  • code
  • 92.17 %
  • assert
  • 95.66 %
  • func
  • 61.49 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 646.096us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 880.311us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 281.979us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 92.498us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 15.907us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 679.539us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 228.349us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 26.156us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 15.907us 1 1 100.00
dma_csr_aliasing 5.000s 228.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 47.000s 3152.782us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 56.000s 21989.325us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 62.000s 10219.403us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 62.000s 10219.403us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 56.000s 21989.325us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 711.000s 75179.623us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 62.000s 10219.403us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 17.000s 971.725us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 214.000s 40392.325us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 15.249us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 66.193us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 290.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 290.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 92.498us 1 1 100.00
dma_csr_rw 1.000s 15.907us 1 1 100.00
dma_csr_aliasing 5.000s 228.349us 1 1 100.00
dma_same_csr_outstanding 3.000s 337.440us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 92.498us 1 1 100.00
dma_csr_rw 1.000s 15.907us 1 1 100.00
dma_csr_aliasing 5.000s 228.349us 1 1 100.00
dma_same_csr_outstanding 3.000s 337.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 319.272us 1 1 100.00
dma_generic_stress 711.000s 75179.623us 1 1 100.00
dma_handshake_stress 62.000s 10219.403us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 345.680us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 39.175us 1 1 100.00
dma_tl_intg_err 3.000s 105.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 53.000s 43877.157us 1 1 100.00
dma_longer_transfer 3.000s 161.956us 1 1 100.00
dma_stress_all_with_rand_reset 14.000s 4038.541us 0 1 0.00