Simulation Results: edn

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 78.36 %
  • assert
  • 94.22 %
  • func
  • 77.29 %
  • line
  • 96.83 %
  • branch
  • 88.27 %
  • cond
  • 83.77 %
  • toggle
  • 71.79 %
  • FSM
  • 51.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 47.097us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 20.093us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 23.056us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.310s 273.952us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 50.231us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.950s 19.892us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 23.056us 1 1 100.00
edn_csr_aliasing 1.040s 50.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 66.272us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 66.272us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 66.272us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.030s 23.120us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.050s 44.211us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 33.014us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 22.553us 1 1 100.00
edn_disable_auto_req_mode 1.160s 99.003us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.090s 250.756us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 23.847us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 113.909us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.810s 125.048us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.810s 125.048us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 20.093us 1 1 100.00
edn_csr_rw 0.750s 23.056us 1 1 100.00
edn_csr_aliasing 1.040s 50.231us 1 1 100.00
edn_same_csr_outstanding 1.190s 30.496us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 20.093us 1 1 100.00
edn_csr_rw 0.750s 23.056us 1 1 100.00
edn_csr_aliasing 1.040s 50.231us 1 1 100.00
edn_same_csr_outstanding 1.190s 30.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.880s 317.946us 1 1 100.00
edn_sec_cm 6.100s 627.379us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 30.451us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.050s 44.211us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.100s 627.379us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.100s 627.379us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.100s 627.379us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.100s 627.379us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.050s 44.211us 1 1 100.00
edn_sec_cm 6.100s 627.379us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.050s 44.211us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.880s 317.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 48.070s 6101.827us 1 1 100.00