Simulation Results: hmac

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.13 %
  • code
  • 97.65 %
  • assert
  • 96.42 %
  • func
  • 43.32 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.62 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.700s 1025.590us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.860s 21.462us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.840s 28.731us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.490s 117.347us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.660s 1013.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.130s 36.058us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.840s 28.731us 1 1 100.00
hmac_csr_aliasing 5.660s 1013.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 3.770s 1500.830us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 58.800s 1438.344us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.770s 234.378us 1 1 100.00
hmac_test_sha384_vectors 427.320s 131736.296us 1 1 100.00
hmac_test_sha512_vectors 392.600s 23130.386us 1 1 100.00
hmac_test_hmac256_vectors 8.960s 2173.605us 1 1 100.00
hmac_test_hmac384_vectors 6.740s 235.885us 1 1 100.00
hmac_test_hmac512_vectors 10.170s 1290.898us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.590s 2305.498us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 796.120s 12933.998us 1 1 100.00
error 1 1 100.00
hmac_error 37.260s 18926.878us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 6.470s 658.408us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.700s 1025.590us 1 1 100.00
hmac_long_msg 3.770s 1500.830us 1 1 100.00
hmac_back_pressure 58.800s 1438.344us 1 1 100.00
hmac_datapath_stress 796.120s 12933.998us 1 1 100.00
hmac_burst_wr 5.590s 2305.498us 1 1 100.00
hmac_stress_all 427.650s 20268.351us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.700s 1025.590us 1 1 100.00
hmac_long_msg 3.770s 1500.830us 1 1 100.00
hmac_back_pressure 58.800s 1438.344us 1 1 100.00
hmac_datapath_stress 796.120s 12933.998us 1 1 100.00
hmac_wipe_secret 6.470s 658.408us 1 1 100.00
hmac_test_sha256_vectors 7.770s 234.378us 1 1 100.00
hmac_test_sha384_vectors 427.320s 131736.296us 1 1 100.00
hmac_test_sha512_vectors 392.600s 23130.386us 1 1 100.00
hmac_test_hmac256_vectors 8.960s 2173.605us 1 1 100.00
hmac_test_hmac384_vectors 6.740s 235.885us 1 1 100.00
hmac_test_hmac512_vectors 10.170s 1290.898us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.700s 1025.590us 1 1 100.00
hmac_long_msg 3.770s 1500.830us 1 1 100.00
hmac_back_pressure 58.800s 1438.344us 1 1 100.00
hmac_datapath_stress 796.120s 12933.998us 1 1 100.00
hmac_burst_wr 5.590s 2305.498us 1 1 100.00
hmac_error 37.260s 18926.878us 1 1 100.00
hmac_wipe_secret 6.470s 658.408us 1 1 100.00
hmac_test_sha256_vectors 7.770s 234.378us 1 1 100.00
hmac_test_sha384_vectors 427.320s 131736.296us 1 1 100.00
hmac_test_sha512_vectors 392.600s 23130.386us 1 1 100.00
hmac_test_hmac256_vectors 8.960s 2173.605us 1 1 100.00
hmac_test_hmac384_vectors 6.740s 235.885us 1 1 100.00
hmac_test_hmac512_vectors 10.170s 1290.898us 1 1 100.00
hmac_stress_all 427.650s 20268.351us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 427.650s 20268.351us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 34.823us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.560s 55.596us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.330s 71.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.330s 71.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.860s 21.462us 1 1 100.00
hmac_csr_rw 0.840s 28.731us 1 1 100.00
hmac_csr_aliasing 5.660s 1013.359us 1 1 100.00
hmac_same_csr_outstanding 1.680s 48.120us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.860s 21.462us 1 1 100.00
hmac_csr_rw 0.840s 28.731us 1 1 100.00
hmac_csr_aliasing 5.660s 1013.359us 1 1 100.00
hmac_same_csr_outstanding 1.680s 48.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.760s 79.319us 1 1 100.00
hmac_tl_intg_err 2.190s 587.529us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.190s 587.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.700s 1025.590us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.940s 32.897us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 58.770s 10860.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.720s 188.837us 1 1 100.00