Simulation Results: lc_ctrl

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.08 %
  • code
  • 88.93 %
  • assert
  • 95.99 %
  • func
  • 88.31 %
  • line
  • 97.64 %
  • branch
  • 96.13 %
  • cond
  • 79.84 %
  • toggle
  • 82.96 %
  • FSM
  • 88.10 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.370s 39.617us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.880s 151.324us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 25.059us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.290s 30.409us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 54.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.170s 19.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 25.059us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 54.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 5.400s 54.972us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.260s 277.883us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.050s 35.779us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 94.141us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.810s 605.219us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_prog_failure 1.970s 94.141us 1 1 100.00
lc_ctrl_errors 4.810s 605.219us 1 1 100.00
lc_ctrl_security_escalation 3.630s 1067.051us 1 1 100.00
lc_ctrl_jtag_state_failure 1.700s 111.375us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.070s 434.025us 1 1 100.00
lc_ctrl_jtag_errors 37.320s 2601.078us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 5.070s 1242.025us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.300s 453.152us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.790s 15135.179us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.710s 1247.345us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.650s 89.164us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.110s 517.278us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 117.112us 1 1 100.00
lc_ctrl_jtag_smoke 6.200s 2310.243us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.010s 451.319us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.070s 434.025us 1 1 100.00
lc_ctrl_jtag_errors 37.320s 2601.078us 1 1 100.00
lc_ctrl_jtag_access 1.200s 58.628us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.610s 4161.143us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.150s 2219.726us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 22.900us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 5.090s 121.623us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 67.541us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.860s 1809.104us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.860s 1809.104us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 151.324us 1 1 100.00
lc_ctrl_csr_rw 0.880s 25.059us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 54.430us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 26.064us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 151.324us 1 1 100.00
lc_ctrl_csr_rw 0.880s 25.059us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 54.430us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 26.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.250s 171.700us 1 1 100.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.250s 171.700us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.260s 277.883us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.900s 295.587us 0 1 0.00
lc_ctrl_sec_cm 6.150s 988.719us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.630s 1067.051us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 5.400s 54.972us 0 1 0.00
lc_ctrl_jtag_state_post_trans 10.010s 451.319us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.890s 4375.648us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.890s 4375.648us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.590s 222.318us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.100s 677.983us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.100s 677.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.670s 2.514us 0 1 0.00