Simulation Results: lc_ctrl

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.46 %
  • code
  • 84.97 %
  • assert
  • 95.99 %
  • func
  • 87.41 %
  • line
  • 97.45 %
  • branch
  • 95.17 %
  • cond
  • 79.47 %
  • toggle
  • 76.01 %
  • FSM
  • 76.74 %
Validation stages
V1
100.00%
V2
85.00%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.570s 35.329us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.170s 21.269us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 18.411us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.950s 104.206us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 185.066us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.430s 50.377us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 18.411us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 185.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.580s 109.848us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.860s 340.743us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.690s 37.435us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.140s 62.460us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 4.110s 132.722us 0 1 0.00
security_escalation 4 7 57.14
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_prog_failure 2.140s 62.460us 1 1 100.00
lc_ctrl_errors 4.110s 132.722us 0 1 0.00
lc_ctrl_security_escalation 8.020s 1068.828us 1 1 100.00
lc_ctrl_jtag_state_failure 10.270s 3724.083us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.220s 746.732us 1 1 100.00
lc_ctrl_jtag_errors 45.130s 10305.966us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.290s 1010.119us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.150s 208.929us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.220s 746.732us 1 1 100.00
lc_ctrl_jtag_errors 45.130s 10305.966us 1 1 100.00
lc_ctrl_jtag_access 5.520s 776.121us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.620s 4301.240us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.080s 361.904us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.410s 159.195us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.650s 761.925us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.290s 1910.189us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.310s 31.903us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.390s 1781.188us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 43.383us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.390s 1116.093us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.120s 17.367us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 26.820s 2565.890us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.970s 59.896us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.510s 34.874us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.510s 34.874us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 21.269us 1 1 100.00
lc_ctrl_csr_rw 0.730s 18.411us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 185.066us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.060s 40.986us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 21.269us 1 1 100.00
lc_ctrl_csr_rw 0.730s 18.411us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 185.066us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.060s 40.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
lc_ctrl_tl_intg_err 1.370s 252.166us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.370s 252.166us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.860s 340.743us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.240s 90.650us 0 1 0.00
lc_ctrl_sec_cm 6.350s 243.796us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.020s 1068.828us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.580s 109.848us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.150s 208.929us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.870s 3538.462us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.870s 3538.462us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.100s 2437.464us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.380s 450.537us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.380s 450.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 40.830s 29204.647us 0 1 0.00