Simulation Results: rom_ctrl

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.47 %
  • code
  • 97.25 %
  • assert
  • 95.49 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 95.10 %
  • toggle
  • 99.46 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.900s 586.977us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.050s 376.748us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.370s 123.554us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.580s 129.897us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 386.912us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.060s 402.258us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.370s 123.554us 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 386.912us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.000s 342.815us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.010s 417.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.350s 649.197us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.960s 502.185us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.600s 227.105us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.970s 1074.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.070s 1543.600us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.070s 1543.600us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.050s 376.748us 1 1 100.00
rom_ctrl_csr_rw 4.370s 123.554us 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 386.912us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.640s 961.829us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.050s 376.748us 1 1 100.00
rom_ctrl_csr_rw 4.370s 123.554us 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 386.912us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.640s 961.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.970s 665.740us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 190.560s 593.891us 0 1 0.00
rom_ctrl_tl_intg_err 41.860s 878.681us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 190.560s 593.891us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 190.560s 593.891us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 190.560s 593.891us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 190.560s 593.891us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.900s 586.977us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.900s 586.977us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.900s 586.977us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.860s 878.681us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
rom_ctrl_kmac_err_chk 6.600s 227.105us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.440s 4513.194us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.970s 665.740us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 190.560s 593.891us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 90.590s 6542.112us 1 1 100.00