Simulation Results: rom_ctrl

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 98.34 %
  • assert
  • 95.49 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 94.50 %
  • toggle
  • 99.21 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.610s 1260.451us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.600s 3354.825us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.390s 1046.640us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.760s 425.956us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 370.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.850s 230.072us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.390s 1046.640us 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 370.849us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.110s 291.788us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.460s 727.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.830s 768.131us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 34.040s 2109.188us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.050s 5590.266us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.620s 399.177us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.470s 726.345us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.470s 726.345us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.600s 3354.825us 1 1 100.00
rom_ctrl_csr_rw 9.390s 1046.640us 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 370.849us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.190s 230.693us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.600s 3354.825us 1 1 100.00
rom_ctrl_csr_rw 9.390s 1046.640us 1 1 100.00
rom_ctrl_csr_aliasing 7.240s 370.849us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.190s 230.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.050s 4312.674us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 451.850s 671.512us 0 1 0.00
rom_ctrl_tl_intg_err 50.390s 1257.446us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 451.850s 671.512us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 451.850s 671.512us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 451.850s 671.512us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 451.850s 671.512us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.610s 1260.451us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.610s 1260.451us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.610s 1260.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.390s 1257.446us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
rom_ctrl_kmac_err_chk 14.050s 5590.266us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.900s 12088.491us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.050s 4312.674us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 451.850s 671.512us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 125.200s 2868.427us 1 1 100.00