Simulation Results: rstmgr

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 99.27 %
  • assert
  • 97.44 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.060s 61.658us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.080s 102.089us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.780s 38.144us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.790s 67.278us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.230s 53.197us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.960s 67.174us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.780s 38.144us 1 1 100.00
rstmgr_csr_aliasing 1.230s 53.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.120s 139.851us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.980s 46.916us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.980s 82.212us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.450s 827.104us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.450s 827.104us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.450s 827.104us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.450s 827.104us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 17.680s 2725.560us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.780s 38.968us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.180s 77.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.180s 77.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.080s 102.089us 1 1 100.00
rstmgr_csr_rw 0.780s 38.144us 1 1 100.00
rstmgr_csr_aliasing 1.230s 53.197us 1 1 100.00
rstmgr_same_csr_outstanding 1.040s 51.840us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.080s 102.089us 1 1 100.00
rstmgr_csr_rw 0.780s 38.144us 1 1 100.00
rstmgr_csr_aliasing 1.230s 53.197us 1 1 100.00
rstmgr_same_csr_outstanding 1.040s 51.840us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 14.400s 3435.400us 1 1 100.00
rstmgr_tl_intg_err 2.460s 339.022us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 14.400s 3435.400us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 14.400s 3435.400us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.460s 339.022us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.000s 59.572us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.400s 447.013us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.860s 292.526us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 14.400s 3435.400us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 38.144us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 38.144us 1 1 100.00