Simulation Results: rv_dm

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.80 %
  • code
  • 72.92 %
  • assert
  • 96.01 %
  • func
  • 58.48 %
  • line
  • 90.69 %
  • branch
  • 74.79 %
  • cond
  • 73.26 %
  • toggle
  • 69.61 %
  • FSM
  • 56.25 %
Validation stages
V1
93.55%
V2
64.29%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 2.150s 1294.256us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.890s 611.381us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.010s 228.980us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 3.640s 17321.153us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 2.300s 631.342us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 5.250s 4725.097us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 5.260s 2442.927us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 26.400s 26285.794us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 289.410s 161191.496us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 2.910s 570.467us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.370s 200.917us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.870s 434.570us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.070s 161.279us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.140s 447.510us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.220s 317.305us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.420s 394.033us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.890s 286.455us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 2.910s 570.467us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.280s 621.151us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.060s 296.690us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.870s 434.570us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.740s 85.026us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.430s 280.782us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.880s 59.091us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 23.780s 16335.897us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 48.160s 3509.197us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.750s 54.543us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 48.160s 3509.197us 1 1 100.00
rv_dm_csr_rw 1.880s 59.091us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 1.000s 125.402us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.910s 61.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 2.150s 1294.256us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.850s 378.993us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 1.000s 229.466us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.240s 259.691us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 2.300s 1172.774us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 78.920s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 299.210s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 525.980s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 246.810s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 1.420s 521.635us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 2.520s 4374.064us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.810s 222.239us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.990s 78.184us 0 1 0.00
tap_ctrl_transitions 1 2 50.00
rv_dm_tap_fsm_rand_reset 1.000s 53.127us 0 1 0.00
rv_dm_tap_fsm 7.270s 6987.540us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.800s 204.080us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 5537.080s 10000000.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.720s 116.906us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 1.000s 15.540us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 1.000s 15.540us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 48.160s 3509.197us 1 1 100.00
rv_dm_csr_hw_reset 1.430s 280.782us 1 1 100.00
rv_dm_csr_rw 1.880s 59.091us 1 1 100.00
rv_dm_same_csr_outstanding 5.830s 1054.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 48.160s 3509.197us 1 1 100.00
rv_dm_csr_hw_reset 1.430s 280.782us 1 1 100.00
rv_dm_csr_rw 1.880s 59.091us 1 1 100.00
rv_dm_same_csr_outstanding 5.830s 1054.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 5.940s 1153.663us 1 1 100.00
rv_dm_sec_cm 3.440s 1501.861us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 5.940s 1153.663us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.520s 4374.064us 1 1 100.00
rv_dm_debug_disabled 1.000s 70.873us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.520s 4374.064us 1 1 100.00
rv_dm_debug_disabled 1.000s 70.873us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 2.150s 1294.256us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 0.950s 142.880us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.970s 61.060us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.970s 61.060us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 0.950s 142.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 1.050s 238.989us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 156.360s 300000.000us 0 1 0.00