Simulation Results: spi_device

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.81 %
  • code
  • 93.17 %
  • assert
  • 86.74 %
  • func
  • 59.52 %
  • line
  • 99.02 %
  • branch
  • 98.18 %
  • cond
  • 95.77 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 25.240s 1685.768us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.970s 104.222us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.170s 72.303us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.810s 2181.477us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.810s 894.133us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.340s 373.582us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.170s 72.303us 1 1 100.00
spi_device_csr_aliasing 9.810s 894.133us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.870s 37.441us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.240s 122.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.840s 56.612us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.720s 6.327us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.680s 5.794us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.180s 126.840us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.180s 126.840us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.170s 703.826us 1 1 100.00
spi_device_tpm_sts_read 0.770s 78.507us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.790s 2569.334us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.760s 486.773us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.490s 1891.415us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.490s 1891.415us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.460s 137.649us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.460s 137.649us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.460s 137.649us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.460s 137.649us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.460s 137.649us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.870s 451.352us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 68.890s 25498.703us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 68.890s 25498.703us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 68.890s 25498.703us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.300s 242.753us 1 1 100.00
spi_device_read_buffer_direct 3.100s 1587.740us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 68.890s 25498.703us 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 111.640s 29049.175us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 21.630s 16471.988us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 21.630s 16471.988us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 25.240s 1685.768us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 40.280s 2893.224us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.120s 105.455us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.700s 64.682us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.710s 33.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.750s 131.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.750s 131.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 104.222us 1 1 100.00
spi_device_csr_rw 2.170s 72.303us 1 1 100.00
spi_device_csr_aliasing 9.810s 894.133us 1 1 100.00
spi_device_same_csr_outstanding 1.630s 25.751us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 104.222us 1 1 100.00
spi_device_csr_rw 2.170s 72.303us 1 1 100.00
spi_device_csr_aliasing 9.810s 894.133us 1 1 100.00
spi_device_same_csr_outstanding 1.630s 25.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 8.500s 390.338us 1 1 100.00
spi_device_sec_cm 1.250s 325.937us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.500s 390.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 26.290s 16671.225us 1 1 100.00