Simulation Results: sram_ctrl

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.12 %
  • code
  • 89.37 %
  • assert
  • 95.55 %
  • func
  • 94.43 %
  • line
  • 97.50 %
  • branch
  • 95.05 %
  • cond
  • 92.29 %
  • toggle
  • 90.59 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.150s 684.762us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.650s 57.204us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.600s 15.332us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.360s 98.233us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 23.321us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.170s 733.973us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.600s 15.332us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 23.321us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 112.980s 6979.580us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 100.370s 2566.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 796.520s 37425.304us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 244.070s 7134.568us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1183.560s 95835.180us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 874.020s 18624.701us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 29.010s 7759.592us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 1009.630s 132805.502us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.440s 471.099us 1 1 100.00
sram_ctrl_partial_access_b2b 214.090s 4802.047us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 52.290s 814.987us 1 1 100.00
sram_ctrl_throughput_w_partial_write 31.720s 962.135us 1 1 100.00
sram_ctrl_throughput_w_readback 11.140s 771.782us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 415.470s 15641.593us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.980s 1409.268us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1695.370s 31865.758us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.660s 50.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.130s 234.704us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.130s 234.704us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.650s 57.204us 1 1 100.00
sram_ctrl_csr_rw 0.600s 15.332us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 23.321us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.640s 31.687us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.650s 57.204us 1 1 100.00
sram_ctrl_csr_rw 0.600s 15.332us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 23.321us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.640s 31.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 53.540s 117197.400us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.650s 2.847us 0 1 0.00
sram_ctrl_tl_intg_err 1.740s 398.409us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.650s 2.847us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.740s 398.409us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 415.470s 15641.593us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 415.470s 15641.593us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.600s 15.332us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 1009.630s 132805.502us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 1009.630s 132805.502us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 1009.630s 132805.502us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 29.010s 7759.592us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.660s 8320.744us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 53.540s 117197.400us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.450s 1351.303us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.150s 684.762us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.150s 684.762us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 1009.630s 132805.502us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.650s 2.847us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 29.010s 7759.592us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.650s 2.847us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 2.847us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.150s 684.762us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 2.847us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.130s 11485.304us 1 1 100.00