Simulation Results: sram_ctrl

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.47 %
  • code
  • 91.52 %
  • assert
  • 95.79 %
  • func
  • 96.10 %
  • line
  • 97.86 %
  • branch
  • 95.71 %
  • cond
  • 92.41 %
  • toggle
  • 90.66 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 9.100s 1148.539us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.640s 47.333us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.514us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.330s 82.027us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 34.691us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.470s 40.612us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.770s 14.514us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 34.691us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.210s 235.602us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.470s 383.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 64.100s 1127.013us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 213.940s 11850.496us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 29.340s 16325.477us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 163.940s 806.280us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.830s 1454.139us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 766.600s 12660.603us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 11.890s 206.201us 1 1 100.00
sram_ctrl_partial_access_b2b 264.930s 15938.910us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 11.910s 309.871us 1 1 100.00
sram_ctrl_throughput_w_partial_write 28.850s 250.447us 1 1 100.00
sram_ctrl_throughput_w_readback 1.050s 47.640us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 618.760s 12433.577us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.760s 105.635us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1597.570s 48354.345us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.690s 19.959us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.730s 789.626us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.730s 789.626us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 47.333us 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.514us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 34.691us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 31.550us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 47.333us 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.514us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 34.691us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 31.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.590s 242.918us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.650s 7.049us 0 1 0.00
sram_ctrl_tl_intg_err 1.220s 430.937us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.650s 7.049us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.220s 430.937us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 618.760s 12433.577us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 618.760s 12433.577us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.514us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 766.600s 12660.603us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 766.600s 12660.603us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 766.600s 12660.603us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.830s 1454.139us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.060s 50.520us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.590s 242.918us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.880s 165.520us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 9.100s 1148.539us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 9.100s 1148.539us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 766.600s 12660.603us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.650s 7.049us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.830s 1454.139us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.650s 7.049us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 7.049us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 9.100s 1148.539us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 7.049us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 246.360s 2842.177us 1 1 100.00