Simulation Results: uart

 
03/12/2025 16:08:58 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.77 %
  • code
  • 95.78 %
  • assert
  • 97.12 %
  • func
  • 55.41 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.190s 280.034us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.840s 15.387us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.810s 13.994us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.500s 549.005us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.970s 24.748us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.790s 44.852us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.810s 13.994us 1 1 100.00
uart_csr_aliasing 0.970s 24.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 12.220s 12330.689us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.190s 280.034us 1 1 100.00
uart_tx_rx 12.220s 12330.689us 1 1 100.00
parity_error 2 2 100.00
uart_intr 37.920s 23645.885us 1 1 100.00
uart_rx_parity_err 41.930s 100805.446us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 12.220s 12330.689us 1 1 100.00
uart_intr 37.920s 23645.885us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 24.950s 150876.055us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 23.110s 70162.955us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 57.680s 61690.458us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 37.920s 23645.885us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 37.920s 23645.885us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 37.920s 23645.885us 1 1 100.00
perf 1 1 100.00
uart_perf 104.340s 12494.499us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 8.690s 9501.957us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 8.690s 9501.957us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 23.820s 17429.097us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.430s 4796.277us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.080s 923.236us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.430s 2211.315us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 184.870s 73758.969us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 235.400s 350011.828us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.720s 17.115us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.710s 10.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.840s 103.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.840s 103.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.840s 15.387us 1 1 100.00
uart_csr_rw 0.810s 13.994us 1 1 100.00
uart_csr_aliasing 0.970s 24.748us 1 1 100.00
uart_same_csr_outstanding 0.760s 76.409us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.840s 15.387us 1 1 100.00
uart_csr_rw 0.810s 13.994us 1 1 100.00
uart_csr_aliasing 0.970s 24.748us 1 1 100.00
uart_same_csr_outstanding 0.760s 76.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.270s 291.138us 1 1 100.00
uart_sec_cm 1.270s 128.222us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.270s 291.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 33.180s 4494.260us 1 1 100.00