Simulation Results: ac_range_check

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.00 %
  • code
  • 93.25 %
  • assert
  • 97.63 %
  • func
  • 58.12 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 81.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 36.000s 7306.323us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 46.000s 6859.231us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 25.656us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 140.457us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 24.000s 1977.234us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1425.462us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 89.544us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 140.457us 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1425.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 25.720us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 32.000s 17736.747us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 157.000s 98872.337us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 43.623us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 44.469us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 4.000s 490.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 4.000s 490.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 25.656us 1 1 100.00
ac_range_check_csr_rw 2.000s 140.457us 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1425.462us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 81.220us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 25.656us 1 1 100.00
ac_range_check_csr_rw 2.000s 140.457us 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1425.462us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 81.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 850.851us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 850.851us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 850.851us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 850.851us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 86.000s 25388.007us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 51.928us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 1050.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 218.000s 5328.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 20.000s 349.968us 1 1 100.00