| chip_sw_spi_device_flash_mode |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
95.826s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through |
1 |
1 |
100.00 |
|
chip_sw_spi_device_pass_through |
2085.150s |
3681.704us |
1 |
1 |
100.00
|
| chip_sw_spi_device_pass_through_collision |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through_collision |
188.800s |
198.849us |
0 |
1 |
0.00
|
| chip_sw_spi_device_tpm |
0 |
1 |
0.00 |
|
chip_sw_spi_device_tpm |
43.305s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_spi_host_tx_rx |
22.825s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_host_tx_rx |
59.022s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_device_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_device_tx_rx |
58.055s |
0.000us |
0 |
1 |
0.00
|
| chip_pin_mux |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
4.010s |
0.000us |
0 |
1 |
0.00
|
| chip_padctrl_attributes |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
4.010s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_wake |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_wake |
115.526s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_retention |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_retention |
115.041s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_data_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
128.882s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_instruction_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
128.882s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_csr_rw |
0 |
1 |
0.00 |
|
chip_jtag_csr_rw |
112.720s |
117.017us |
0 |
1 |
0.00
|
| chip_jtag_mem_access |
0 |
1 |
0.00 |
|
chip_jtag_mem_access |
116.210s |
117.032us |
0 |
1 |
0.00
|
| chip_rv_dm_ndm_reset_req |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
246.800s |
272.534us |
1 |
1 |
100.00
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
9.838s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_access_after_wakeup |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_access_after_wakeup |
10.965s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_lc_disabled |
0 |
1 |
0.00 |
|
chip_rv_dm_lc_disabled |
88.010s |
129.272us |
0 |
1 |
0.00
|
| chip_sw_timer |
1 |
1 |
100.00 |
|
chip_sw_rv_timer_irq |
255.250s |
248.728us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wakeup_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
453.470s |
505.554us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_bark_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
453.470s |
505.554us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_lc_escalate |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_wdog_lc_escalate |
360.150s |
348.467us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.760s |
164.371us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.760s |
164.371us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_sleep_pause |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_sleep_wdog_sleep_pause |
291.090s |
2271.442us |
1 |
1 |
100.00
|
| chip_sw_plic_sw_irq |
1 |
1 |
100.00 |
|
chip_sw_plic_sw_irq |
156.860s |
145.502us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_idle_trans |
4 |
4 |
100.00 |
|
chip_sw_otbn_randomness |
259.750s |
225.611us |
1 |
1 |
100.00
|
|
chip_sw_aes_idle |
169.400s |
147.279us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_idle |
198.270s |
161.507us |
1 |
1 |
100.00
|
|
chip_sw_kmac_idle |
153.490s |
145.039us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_off_trans |
0 |
4 |
0.00 |
|
chip_sw_clkmgr_off_aes_trans |
161.170s |
165.712us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_hmac_trans |
181.760s |
165.632us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_kmac_trans |
161.460s |
165.680us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_otbn_trans |
158.530s |
165.664us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
36.440s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.790s |
10.260us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
40.310s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.450s |
10.320us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
38.260s |
10.340us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
12.562s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
149.490s |
141.904us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_extended_range |
1 |
8 |
12.50 |
|
chip_sw_clkmgr_jitter_reduced_freq |
295.660s |
1779.447us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
38.980s |
10.300us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
36.970s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
38.910s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq |
37.470s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
44.510s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
44.220s |
10.300us |
0 |
1 |
0.00
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
35.900s |
10.380us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_deep_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
9.953s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_sleep_frequency |
10.666s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_reset_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_reset_frequency |
12.659s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
851.040s |
905.498us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_external_full_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
358.970s |
491.146us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_sleep_all_reset_reqs |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
204.760s |
164.371us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_wdog_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_wdog_reset |
12.672s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_aon_power_glitch_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
358.970s |
491.146us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_main_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_main_power_glitch_reset |
11.094s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
9.323s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
9.168s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_power_glitch_reset |
11.334s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_disabled |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_disabled |
9.857s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
851.040s |
905.498us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sys_reset_info |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
246.800s |
272.534us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_cpu_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
360.410s |
375.408us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_req_reset |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_req |
261.150s |
267.296us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_alert_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
323.920s |
290.006us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_rst |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_rst |
184.350s |
144.103us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
851.040s |
905.498us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_test |
12.496s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_escalations |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
12.650s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_all_escalation_resets |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
851.040s |
905.498us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_entropy |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_entropy |
9.780s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_crashdump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
323.920s |
290.006us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_ping_timeout |
1 |
1 |
100.00 |
|
chip_sw_alert_handler_ping_timeout |
297.350s |
331.626us |
1 |
1 |
100.00
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_alerts |
10.448s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_sleep_mode_pings |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_pings |
11.642s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_clock_off |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_clkoff |
10.015s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_reset_toggle |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_reset_toggle |
10.189s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
10.118s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_alert_handler_escalation |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
12.650s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_jtag_access |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_otp_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
12.851s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_transitions |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_kmac_req |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_key_div |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation_prod |
271.510s |
267.648us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_broadcast |
2 |
10 |
20.00 |
|
chip_prim_tl_access |
677.540s |
1093.882us |
1 |
1 |
100.00
|
|
chip_rv_dm_lc_disabled |
88.010s |
129.272us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
13.467s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
22.458s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
21.718s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
17.906s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation |
282.050s |
267.837us |
0 |
1 |
0.00
|
|
chip_sw_rom_ctrl_integrity_check |
704.120s |
1266.541us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_execution_main |
11.160s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_aes_enc |
1 |
2 |
50.00 |
|
chip_sw_aes_enc |
175.930s |
157.108us |
1 |
1 |
100.00
|
|
chip_sw_aes_enc_jitter_en |
36.790s |
10.260us |
0 |
1 |
0.00
|
| chip_sw_aes_entropy |
1 |
1 |
100.00 |
|
chip_sw_aes_entropy |
151.650s |
145.857us |
1 |
1 |
100.00
|
| chip_sw_aes_idle |
1 |
1 |
100.00 |
|
chip_sw_aes_idle |
169.400s |
147.279us |
1 |
1 |
100.00
|
| chip_sw_hmac_enc |
1 |
2 |
50.00 |
|
chip_sw_hmac_enc |
185.550s |
156.415us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_jitter_en |
40.310s |
10.200us |
0 |
1 |
0.00
|
| chip_sw_hmac_idle |
1 |
1 |
100.00 |
|
chip_sw_hmac_enc_idle |
198.270s |
161.507us |
1 |
1 |
100.00
|
| chip_sw_kmac_enc |
2 |
3 |
66.67 |
|
chip_sw_kmac_mode_cshake |
174.580s |
148.938us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac |
209.930s |
172.139us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
38.260s |
10.340us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_keymgr |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
282.050s |
267.837us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_lc |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_rom |
0 |
1 |
0.00 |
|
chip_sw_kmac_app_rom |
33.080s |
10.140us |
0 |
1 |
0.00
|
| chip_sw_kmac_entropy |
1 |
1 |
100.00 |
|
chip_sw_kmac_entropy |
243.710s |
184.890us |
1 |
1 |
100.00
|
| chip_sw_kmac_idle |
1 |
1 |
100.00 |
|
chip_sw_kmac_idle |
153.490s |
145.039us |
1 |
1 |
100.00
|
| chip_sw_entropy_src_csrng |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
351.540s |
258.274us |
1 |
1 |
100.00
|
| chip_sw_csrng_edn_cmd |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
351.540s |
258.274us |
1 |
1 |
100.00
|
| chip_sw_csrng_fuse_en_sw_app_read |
0 |
1 |
0.00 |
|
chip_sw_csrng_fuse_en_sw_app_read_test |
12.181s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_csrng_known_answer_tests |
1 |
1 |
100.00 |
|
chip_sw_csrng_kat_test |
180.250s |
156.802us |
1 |
1 |
100.00
|
| chip_sw_edn_entropy_reqs |
1 |
1 |
100.00 |
|
chip_sw_csrng_edn_concurrency |
1431.080s |
1288.135us |
1 |
1 |
100.00
|
| chip_sw_keymgr_dpe_key_derivation |
0 |
2 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
282.050s |
267.837us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.450s |
10.320us |
0 |
1 |
0.00
|
| chip_sw_otbn_op |
1 |
2 |
50.00 |
|
chip_sw_otbn_ecdsa_op_irq |
2254.760s |
1468.699us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
36.440s |
10.120us |
0 |
1 |
0.00
|
| chip_sw_otbn_rnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
259.750s |
225.611us |
1 |
1 |
100.00
|
| chip_sw_otbn_urnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
259.750s |
225.611us |
1 |
1 |
100.00
|
| chip_sw_otbn_idle |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
259.750s |
225.611us |
1 |
1 |
100.00
|
| chip_sw_otbn_mem_scramble |
1 |
1 |
100.00 |
|
chip_sw_otbn_mem_scramble |
372.050s |
264.674us |
1 |
1 |
100.00
|
| chip_sw_rom_access |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
704.120s |
1266.541us |
1 |
1 |
100.00
|
| chip_sw_rom_ctrl_integrity_check |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
704.120s |
1266.541us |
1 |
1 |
100.00
|
| chip_sw_sram_scrambled_access |
1 |
2 |
50.00 |
|
chip_sw_sram_ctrl_scrambled_access |
301.760s |
314.014us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
12.562s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_execution |
0 |
1 |
0.00 |
|
chip_sw_sram_ctrl_execution_main |
11.160s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_lc_escalation |
0 |
2 |
0.00 |
|
chip_sw_all_escalation_resets |
851.040s |
905.498us |
0 |
1 |
0.00
|
|
chip_sw_data_integrity_escalation |
128.882s |
0.000us |
0 |
1 |
0.00
|
| chip_otp_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_keys |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
372.050s |
264.674us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
282.050s |
267.837us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
301.760s |
314.014us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
150.780s |
160.188us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_entropy |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
372.050s |
264.674us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
282.050s |
267.837us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
301.760s |
314.014us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
150.780s |
160.188us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_program |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program_error |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_program_error |
11.338s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
12.851s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_lc_signals |
1 |
6 |
16.67 |
|
chip_prim_tl_access |
677.540s |
1093.882us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
13.467s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
22.458s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
21.718s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
17.906s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
11.687s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_prim_tl_access |
1 |
1 |
100.00 |
|
chip_prim_tl_access |
677.540s |
1093.882us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_nvm_cnt |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_nvm_cnt |
15.450s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_sw_parts |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_sw_parts |
15.574s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_clk_outputs |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
9.953s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_sys_clk_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
36.440s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.790s |
10.260us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
40.310s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.450s |
10.320us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
38.260s |
10.340us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
12.562s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
149.490s |
141.904us |
1 |
1 |
100.00
|
| chip_sw_soc_proxy_external_reset_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
146.990s |
143.536us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_irqs |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
146.990s |
143.536us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_wakeup_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_external_wakeup |
148.400s |
138.800us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_gpios |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_gpios |
159.110s |
136.482us |
0 |
1 |
0.00
|
| chip_sw_nmi_irq |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_nmi_irq |
340.830s |
251.582us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_rnd |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_rnd |
187.620s |
172.464us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_address_translation |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_address_translation |
172.210s |
164.753us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_icache_scrambled_access |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_icache_invalidate |
150.780s |
160.188us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_fault_dump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
360.410s |
375.408us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_double_fault |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
360.410s |
375.408us |
0 |
1 |
0.00
|
| chip_sw_smoketest |
14 |
14 |
100.00 |
|
chip_sw_aes_smoketest |
148.120s |
157.103us |
1 |
1 |
100.00
|
|
chip_sw_aon_timer_smoketest |
148.300s |
163.300us |
1 |
1 |
100.00
|
|
chip_sw_clkmgr_smoketest |
123.470s |
142.954us |
1 |
1 |
100.00
|
|
chip_sw_csrng_smoketest |
123.680s |
144.776us |
1 |
1 |
100.00
|
|
chip_sw_gpio_smoketest |
141.180s |
165.790us |
1 |
1 |
100.00
|
|
chip_sw_hmac_smoketest |
160.540s |
182.035us |
1 |
1 |
100.00
|
|
chip_sw_kmac_smoketest |
152.800s |
171.097us |
1 |
1 |
100.00
|
|
chip_sw_otbn_smoketest |
176.400s |
193.037us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_smoketest |
130.180s |
146.892us |
1 |
1 |
100.00
|
|
chip_sw_rv_plic_smoketest |
124.680s |
145.100us |
1 |
1 |
100.00
|
|
chip_sw_rv_timer_smoketest |
188.480s |
248.764us |
1 |
1 |
100.00
|
|
chip_sw_rstmgr_smoketest |
116.290s |
141.625us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_smoketest |
123.780s |
145.487us |
1 |
1 |
100.00
|
|
chip_sw_uart_smoketest |
136.580s |
155.821us |
1 |
1 |
100.00
|
| chip_sw_rom_functests |
0 |
1 |
0.00 |
|
rom_keymgr_functest |
10.170s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_signed |
0 |
1 |
0.00 |
|
chip_sw_uart_smoketest_signed |
10.097s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_boot |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
95.826s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_secure_boot |
0 |
1 |
0.00 |
|
base_rom_e2e_smoke |
10.741s |
0.000us |
0 |
1 |
0.00
|
| chip_lc_scrap |
4 |
4 |
100.00 |
|
chip_sw_lc_ctrl_rma_to_scrap |
214.450s |
229.720us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_raw_to_scrap |
164.710s |
213.002us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
164.690s |
219.295us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_rand_to_scrap |
168.040s |
214.937us |
1 |
1 |
100.00
|
| chip_lc_test_locked |
0 |
2 |
0.00 |
|
chip_rv_dm_lc_disabled |
88.010s |
129.272us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
12.906s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_walkthrough |
0 |
5 |
0.00 |
|
chip_sw_lc_walkthrough_dev |
14.134s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prod |
18.026s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prodend |
9.813s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_rma |
14.831s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
12.906s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_volatile_raw_unlock |
2 |
3 |
66.67 |
|
chip_sw_lc_ctrl_volatile_raw_unlock |
435.280s |
554.292us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
435.140s |
544.664us |
1 |
1 |
100.00
|
|
rom_volatile_raw_unlock |
9.709s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_raw_unlock |
0 |
1 |
0.00 |
|
rom_raw_unlock |
10.944s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_exit_test_unlocked_bootstrap |
0 |
1 |
0.00 |
|
chip_sw_exit_test_unlocked_bootstrap |
77.413s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_inject_scramble_seed |
0 |
1 |
0.00 |
|
chip_sw_inject_scramble_seed |
84.298s |
0.000us |
0 |
1 |
0.00
|
| tl_d_oob_addr_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
101.850s |
118.200us |
0 |
1 |
0.00
|
| tl_d_illegal_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
101.850s |
118.200us |
0 |
1 |
0.00
|
| tl_d_outstanding_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.420s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
11.460s |
0.000us |
0 |
1 |
0.00
|
| tl_d_partial_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.420s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
11.460s |
0.000us |
0 |
1 |
0.00
|
| xbar_base_random_sequence |
1 |
1 |
100.00 |
|
xbar_random |
60.180s |
51.842us |
1 |
1 |
100.00
|
| xbar_random_delay |
6 |
6 |
100.00 |
|
xbar_smoke_zero_delays |
7.770s |
11.421us |
1 |
1 |
100.00
|
|
xbar_smoke_large_delays |
306.370s |
2443.988us |
1 |
1 |
100.00
|
|
xbar_smoke_slow_rsp |
368.750s |
2144.407us |
1 |
1 |
100.00
|
|
xbar_random_zero_delays |
93.370s |
73.932us |
1 |
1 |
100.00
|
|
xbar_random_large_delays |
989.390s |
7851.691us |
1 |
1 |
100.00
|
|
xbar_random_slow_rsp |
1119.680s |
6361.757us |
1 |
1 |
100.00
|
| xbar_unmapped_address |
2 |
2 |
100.00 |
|
xbar_unmapped_addr |
67.150s |
108.530us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
103.470s |
207.562us |
1 |
1 |
100.00
|
| xbar_error_cases |
2 |
2 |
100.00 |
|
xbar_error_random |
31.020s |
33.495us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
103.470s |
207.562us |
1 |
1 |
100.00
|
| xbar_all_access_same_device |
2 |
2 |
100.00 |
|
xbar_access_same_device |
47.220s |
102.144us |
1 |
1 |
100.00
|
|
xbar_access_same_device_slow_rsp |
3530.270s |
22389.015us |
1 |
1 |
100.00
|
| xbar_all_hosts_use_same_source_id |
1 |
1 |
100.00 |
|
xbar_same_source |
49.420s |
133.272us |
1 |
1 |
100.00
|
| xbar_stress_all |
2 |
2 |
100.00 |
|
xbar_stress_all |
490.740s |
1136.172us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_error |
361.440s |
361.173us |
1 |
1 |
100.00
|
| xbar_stress_with_reset |
2 |
2 |
100.00 |
|
xbar_stress_all_with_rand_reset |
1658.050s |
3987.370us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_reset_error |
537.880s |
357.490us |
1 |
1 |
100.00
|
| rom_e2e_smoke |
0 |
1 |
0.00 |
|
rom_e2e_smoke |
10.081s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_output |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_output |
11.040s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_exception_c |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_exception_c |
10.967s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_boot_policy_valid |
0 |
15 |
0.00 |
|
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
9.493s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
11.442s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
11.487s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
10.428s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
11.465s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
10.501s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
10.425s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
9.999s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
10.379s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
9.522s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
66.105s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
50.385s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
74.845s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
72.971s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
73.073s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_sigverify_always |
0 |
15 |
0.00 |
|
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
75.445s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
59.061s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
53.672s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
59.108s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
65.235s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
67.259s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
69.732s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
64.642s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
49.460s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
41.946s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
20.648s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
12.074s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
16.527s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
29.886s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
14.338s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_asm_init |
0 |
5 |
0.00 |
|
rom_e2e_asm_init_test_unlocked0 |
15.033s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_dev |
13.520s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod |
24.348s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod_end |
10.462s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_rma |
12.362s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_keymgr_init |
0 |
3 |
0.00 |
|
rom_e2e_keymgr_init_rom_ext_meas |
9.228s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
9.817s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
13.449s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_static_critical |
0 |
1 |
0.00 |
|
rom_e2e_static_critical |
10.976s |
0.000us |
0 |
1 |
0.00
|