Simulation Results: clkmgr

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.76 %
  • code
  • 69.35 %
  • assert
  • 89.05 %
  • func
  • 59.89 %
  • line
  • 82.34 %
  • branch
  • 87.58 %
  • cond
  • 78.36 %
  • toggle
  • 98.49 %
  • FSM
  • 0.00 %
Validation stages
V1
25.00%
V2
47.37%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.050s 50.943us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.890s 44.498us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.090s 54.986us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.720s 13.915us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.610s 2.020us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
clkmgr_csr_aliasing 0.720s 13.915us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.770s 29.779us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.390s 94.919us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 50.781us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.050s 50.943us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.690s 14.707us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.600s 2.935us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.690s 14.707us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.790s 25.725us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.270s 95.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.650s 89.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.650s 89.461us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.890s 44.498us 1 1 100.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
clkmgr_csr_aliasing 0.720s 13.915us 0 1 0.00
clkmgr_same_csr_outstanding 0.660s 7.207us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.890s 44.498us 1 1 100.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
clkmgr_csr_aliasing 0.720s 13.915us 0 1 0.00
clkmgr_same_csr_outstanding 0.660s 7.207us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.090s 687.645us 1 1 100.00
clkmgr_tl_intg_err 0.540s 1.701us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 78.461us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 78.461us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 78.461us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 78.461us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.710s 10.569us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.540s 1.701us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.690s 14.707us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.600s 2.935us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 78.461us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.100s 198.294us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.090s 687.645us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.590s 4.177us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.090s 687.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.680s 7.394us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.800s 21.376us 0 1 0.00