Simulation Results: dma

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.41 %
  • code
  • 92.17 %
  • assert
  • 95.55 %
  • func
  • 62.51 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 698.035us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 479.768us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 320.965us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 31.883us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 16.204us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 5.000s 159.321us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 1347.511us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 102.749us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 16.204us 1 1 100.00
dma_csr_aliasing 4.000s 1347.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 93.000s 5318.775us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 300.000s 96455.118us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 108.000s 8771.135us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 108.000s 8771.135us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 300.000s 96455.118us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 613.000s 212604.872us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 108.000s 8771.135us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 423.425us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 209.000s 15329.221us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 22.578us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 19.825us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 108.845us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 108.845us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 31.883us 1 1 100.00
dma_csr_rw 1.000s 16.204us 1 1 100.00
dma_csr_aliasing 4.000s 1347.511us 1 1 100.00
dma_same_csr_outstanding 3.000s 763.554us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 31.883us 1 1 100.00
dma_csr_rw 1.000s 16.204us 1 1 100.00
dma_csr_aliasing 4.000s 1347.511us 1 1 100.00
dma_same_csr_outstanding 3.000s 763.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 1133.360us 1 1 100.00
dma_generic_stress 613.000s 212604.872us 1 1 100.00
dma_handshake_stress 108.000s 8771.135us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 9.000s 345.706us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 2.000s 17.939us 1 1 100.00
dma_tl_intg_err 3.000s 121.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 132.000s 32043.532us 1 1 100.00
dma_longer_transfer 4.000s 106.105us 1 1 100.00
dma_stress_all_with_rand_reset 10.000s 492.036us 0 1 0.00