Simulation Results: edn

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.81 %
  • code
  • 82.01 %
  • assert
  • 96.22 %
  • func
  • 79.20 %
  • line
  • 97.96 %
  • branch
  • 92.82 %
  • cond
  • 87.62 %
  • toggle
  • 81.65 %
  • FSM
  • 50.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 47.022us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.030s 29.352us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.090s 23.403us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.730s 420.104us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.390s 20.527us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 224.396us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.090s 23.403us 1 1 100.00
edn_csr_aliasing 1.390s 20.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.990s 69.835us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.990s 69.835us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.990s 69.835us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 26.409us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 42.003us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 38.252us 1 1 100.00
disable 2 2 100.00
edn_disable 0.830s 46.949us 1 1 100.00
edn_disable_auto_req_mode 1.140s 61.274us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.760s 163.944us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.040s 52.558us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.940s 45.799us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.390s 51.259us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.390s 51.259us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.030s 29.352us 1 1 100.00
edn_csr_rw 1.090s 23.403us 1 1 100.00
edn_csr_aliasing 1.390s 20.527us 1 1 100.00
edn_same_csr_outstanding 1.080s 52.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.030s 29.352us 1 1 100.00
edn_csr_rw 1.090s 23.403us 1 1 100.00
edn_csr_aliasing 1.390s 20.527us 1 1 100.00
edn_same_csr_outstanding 1.080s 52.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.020s 91.068us 1 1 100.00
edn_sec_cm 4.280s 2223.141us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 19.548us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 42.003us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.280s 2223.141us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.280s 2223.141us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.280s 2223.141us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.280s 2223.141us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 42.003us 1 1 100.00
edn_sec_cm 4.280s 2223.141us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 42.003us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.020s 91.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 50.480s 29198.654us 1 1 100.00