Simulation Results: hmac

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.98 %
  • code
  • 97.94 %
  • assert
  • 96.42 %
  • func
  • 42.57 %
  • line
  • 99.68 %
  • branch
  • 99.34 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.600s 2011.590us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 313.527us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.780s 43.579us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.940s 975.742us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.880s 203.595us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.520s 37.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.780s 43.579us 1 1 100.00
hmac_csr_aliasing 2.880s 203.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 27.040s 7205.318us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 16.750s 416.660us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 201.590s 5699.562us 1 1 100.00
hmac_test_sha384_vectors 22.420s 234.263us 1 1 100.00
hmac_test_sha512_vectors 31.560s 208.675us 1 1 100.00
hmac_test_hmac256_vectors 10.170s 315.239us 1 1 100.00
hmac_test_hmac384_vectors 8.230s 1345.717us 1 1 100.00
hmac_test_hmac512_vectors 13.490s 2294.974us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.390s 1551.327us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 34.070s 940.917us 1 1 100.00
error 1 1 100.00
hmac_error 56.380s 4068.893us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 35.400s 5316.498us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.600s 2011.590us 1 1 100.00
hmac_long_msg 27.040s 7205.318us 1 1 100.00
hmac_back_pressure 16.750s 416.660us 1 1 100.00
hmac_datapath_stress 34.070s 940.917us 1 1 100.00
hmac_burst_wr 5.390s 1551.327us 1 1 100.00
hmac_stress_all 373.810s 27030.362us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.600s 2011.590us 1 1 100.00
hmac_long_msg 27.040s 7205.318us 1 1 100.00
hmac_back_pressure 16.750s 416.660us 1 1 100.00
hmac_datapath_stress 34.070s 940.917us 1 1 100.00
hmac_wipe_secret 35.400s 5316.498us 1 1 100.00
hmac_test_sha256_vectors 201.590s 5699.562us 1 1 100.00
hmac_test_sha384_vectors 22.420s 234.263us 1 1 100.00
hmac_test_sha512_vectors 31.560s 208.675us 1 1 100.00
hmac_test_hmac256_vectors 10.170s 315.239us 1 1 100.00
hmac_test_hmac384_vectors 8.230s 1345.717us 1 1 100.00
hmac_test_hmac512_vectors 13.490s 2294.974us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.600s 2011.590us 1 1 100.00
hmac_long_msg 27.040s 7205.318us 1 1 100.00
hmac_back_pressure 16.750s 416.660us 1 1 100.00
hmac_datapath_stress 34.070s 940.917us 1 1 100.00
hmac_burst_wr 5.390s 1551.327us 1 1 100.00
hmac_error 56.380s 4068.893us 1 1 100.00
hmac_wipe_secret 35.400s 5316.498us 1 1 100.00
hmac_test_sha256_vectors 201.590s 5699.562us 1 1 100.00
hmac_test_sha384_vectors 22.420s 234.263us 1 1 100.00
hmac_test_sha512_vectors 31.560s 208.675us 1 1 100.00
hmac_test_hmac256_vectors 10.170s 315.239us 1 1 100.00
hmac_test_hmac384_vectors 8.230s 1345.717us 1 1 100.00
hmac_test_hmac512_vectors 13.490s 2294.974us 1 1 100.00
hmac_stress_all 373.810s 27030.362us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 373.810s 27030.362us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.640s 42.635us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 16.523us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.320s 47.239us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.320s 47.239us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 313.527us 1 1 100.00
hmac_csr_rw 0.780s 43.579us 1 1 100.00
hmac_csr_aliasing 2.880s 203.595us 1 1 100.00
hmac_same_csr_outstanding 1.140s 20.939us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 313.527us 1 1 100.00
hmac_csr_rw 0.780s 43.579us 1 1 100.00
hmac_csr_aliasing 2.880s 203.595us 1 1 100.00
hmac_same_csr_outstanding 1.140s 20.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 4.360s 288.163us 1 1 100.00
hmac_sec_cm 1.070s 42.903us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.360s 288.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.600s 2011.590us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.030s 219.615us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 37.190s 10216.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.330s 40.364us 1 1 100.00