Simulation Results: i2c

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.48 %
  • code
  • 81.12 %
  • assert
  • 96.41 %
  • func
  • 81.92 %
  • line
  • 96.35 %
  • branch
  • 92.19 %
  • cond
  • 84.55 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 17.290s 1569.453us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 23.390s 1199.951us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.660s 59.887us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.660s 25.718us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.860s 767.139us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.410s 115.039us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.750s 25.951us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.660s 25.718us 1 1 100.00
i2c_csr_aliasing 1.410s 115.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.660s 18.056us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 627.940s 68106.134us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 185.060s 25430.277us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.610s 14.894us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 241.160s 5438.051us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 99.570s 4603.585us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.850s 193.907us 1 1 100.00
i2c_host_fifo_fmt_empty 3.440s 922.182us 1 1 100.00
i2c_host_fifo_reset_rx 3.360s 2970.182us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 38.750s 11021.025us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.290s 730.500us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.940s 184.562us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.940s 7078.774us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 291.860s 59035.036us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.750s 668.221us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 5.430s 2587.496us 1 1 100.00
i2c_target_intr_smoke 5.020s 22604.275us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.680s 180.663us 1 1 100.00
i2c_target_fifo_reset_tx 1.400s 321.107us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 50.840s 57270.663us 1 1 100.00
i2c_target_stress_rd 5.430s 2587.496us 1 1 100.00
i2c_target_intr_stress_wr 28.640s 30526.996us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.140s 5194.380us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 20.700s 1433.014us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.970s 12665.374us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.810s 1341.022us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.750s 838.470us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.930s 114.669us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 185.060s 25430.277us 1 1 100.00
i2c_host_perf_precise 122.340s 23979.955us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.290s 730.500us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.130s 189.350us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.740s 543.692us 1 1 100.00
i2c_target_nack_acqfull_addr 1.690s 825.169us 1 1 100.00
i2c_target_nack_txstretch 1.000s 260.739us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 2.810s 584.209us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.650s 514.927us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.670s 20.676us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.700s 53.611us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.200s 263.229us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.200s 263.229us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.660s 59.887us 1 1 100.00
i2c_csr_rw 0.660s 25.718us 1 1 100.00
i2c_csr_aliasing 1.410s 115.039us 1 1 100.00
i2c_same_csr_outstanding 0.720s 58.464us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.660s 59.887us 1 1 100.00
i2c_csr_rw 0.660s 25.718us 1 1 100.00
i2c_csr_aliasing 1.410s 115.039us 1 1 100.00
i2c_same_csr_outstanding 0.720s 58.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.570s 174.584us 1 1 100.00
i2c_sec_cm 0.740s 146.450us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.570s 174.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 7.450s 1510.871us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.150s 854.939us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 22.240s 892.001us 0 1 0.00