Simulation Results: lc_ctrl

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.76 %
  • code
  • 87.62 %
  • assert
  • 95.99 %
  • func
  • 88.67 %
  • line
  • 97.80 %
  • branch
  • 96.56 %
  • cond
  • 79.84 %
  • toggle
  • 82.93 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.910s 68.759us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 47.997us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.160s 31.916us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.540s 160.135us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 68.717us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.960s 20.588us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.160s 31.916us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 68.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.300s 25.801us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.100s 1313.722us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 14.498us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.180s 56.032us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.540s 989.348us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_prog_failure 2.180s 56.032us 1 1 100.00
lc_ctrl_errors 8.540s 989.348us 1 1 100.00
lc_ctrl_security_escalation 6.130s 244.308us 1 1 100.00
lc_ctrl_jtag_state_failure 6.500s 639.926us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.570s 236.126us 1 1 100.00
lc_ctrl_jtag_errors 24.650s 2845.105us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.230s 469.632us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.480s 57.585us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.810s 761.588us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.160s 1436.855us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.070s 120.470us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.500s 594.887us 1 1 100.00
lc_ctrl_jtag_alert_test 0.850s 42.284us 1 1 100.00
lc_ctrl_jtag_smoke 4.640s 218.538us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.070s 1204.669us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.570s 236.126us 1 1 100.00
lc_ctrl_jtag_errors 24.650s 2845.105us 1 1 100.00
lc_ctrl_jtag_access 3.770s 836.989us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.060s 756.038us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.870s 351.461us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 37.878us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 17.510s 1282.499us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.770s 91.680us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.410s 62.845us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.410s 62.845us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 47.997us 1 1 100.00
lc_ctrl_csr_rw 1.160s 31.916us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 68.717us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 560.424us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 47.997us 1 1 100.00
lc_ctrl_csr_rw 1.160s 31.916us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 68.717us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 560.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.150s 92.612us 1 1 100.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.150s 92.612us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.100s 1313.722us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 2.930s 22.402us 0 1 0.00
lc_ctrl_sec_cm 7.560s 949.520us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.130s 244.308us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.300s 25.801us 0 1 0.00
lc_ctrl_jtag_state_post_trans 6.070s 1204.669us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.500s 357.015us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.500s 357.015us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.420s 1044.212us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.310s 953.237us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.310s 953.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.360s 1993.504us 0 1 0.00