Simulation Results: lc_ctrl

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.09 %
  • code
  • 88.66 %
  • assert
  • 95.99 %
  • func
  • 85.61 %
  • line
  • 97.50 %
  • branch
  • 96.01 %
  • cond
  • 78.75 %
  • toggle
  • 82.69 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.010s 274.305us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.970s 16.198us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 151.611us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.460s 500.898us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 37.044us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 79.358us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 151.611us 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 37.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 2.360s 1055.214us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.920s 2184.925us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 58.321us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.360s 257.121us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.420s 1518.696us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_prog_failure 2.360s 257.121us 1 1 100.00
lc_ctrl_errors 5.420s 1518.696us 1 1 100.00
lc_ctrl_security_escalation 5.730s 251.539us 1 1 100.00
lc_ctrl_jtag_state_failure 2.080s 195.861us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.740s 395.517us 1 1 100.00
lc_ctrl_jtag_errors 46.920s 11731.081us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.370s 51.019us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.300s 42.800us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 1595.135us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.500s 718.560us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.820s 31.522us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.630s 238.326us 1 1 100.00
lc_ctrl_jtag_alert_test 0.890s 133.636us 1 1 100.00
lc_ctrl_jtag_smoke 1.640s 212.894us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.960s 155.242us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.740s 395.517us 1 1 100.00
lc_ctrl_jtag_errors 46.920s 11731.081us 1 1 100.00
lc_ctrl_jtag_access 5.480s 679.809us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.530s 848.969us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.020s 562.168us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.070s 16.008us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 64.100s 10850.732us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 48.062us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.280s 124.592us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.280s 124.592us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 16.198us 1 1 100.00
lc_ctrl_csr_rw 0.860s 151.611us 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 37.044us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 37.780us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 16.198us 1 1 100.00
lc_ctrl_csr_rw 0.860s 151.611us 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 37.044us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 37.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.260s 65.966us 1 1 100.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 65.966us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.920s 2184.925us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.240s 32.968us 0 1 0.00
lc_ctrl_sec_cm 7.890s 247.441us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.730s 251.539us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 2.360s 1055.214us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3.960s 155.242us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.520s 1725.724us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.520s 1725.724us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.110s 364.209us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.490s 717.335us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.490s 717.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.850s 3910.320us 0 1 0.00